imximage.cfg 4.3 KB

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  1. /*
  2. * Copyright (C) 2014 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. *
  6. * Refer docs/README.imxmage for more details about how-to configure
  7. * and create imximage boot image
  8. *
  9. * The syntax is taken as close as possible with the kwbimage
  10. */
  11. #define __ASSEMBLY__
  12. #include <config.h>
  13. /* image version */
  14. IMAGE_VERSION 2
  15. /*
  16. * Boot Device : sd
  17. */
  18. BOOT_FROM sd
  19. /*
  20. * Secure boot support
  21. */
  22. #ifdef CONFIG_IMX_HAB
  23. CSF CONFIG_CSF_SIZE
  24. #endif
  25. /*
  26. * Device Configuration Data (DCD)
  27. *
  28. * Each entry must have the format:
  29. * Addr-type Address Value
  30. *
  31. * where:
  32. * Addr-type register length (1,2 or 4 bytes)
  33. * Address absolute address of the register
  34. * value value to be stored in the register
  35. */
  36. /* Enable OCRAM EPDC */
  37. DATA 4 0x30340004 0x4F400005
  38. /* =============================================================================
  39. * DDR Controller Registers
  40. * =============================================================================
  41. * Memory type: DDR3
  42. * Manufacturer: ISSI
  43. * Device Part Number: IS43TR16256AL-125KBL
  44. * Clock Freq.: 533MHz
  45. * Density per CS in Gb: 4
  46. * Chip Selects used: 1
  47. * Number of Banks: 8
  48. * Row address: 15
  49. * Column address: 10
  50. * Data bus width: 16
  51. * ROW-BANK interleave: ENABLED
  52. * =============================================================================
  53. */
  54. DATA 4 0x30391000 0x00000002 // deassert presetn
  55. DATA 4 0x307A0000 0x01041001 // DDRC_MSTR
  56. DATA 4 0x307A0064 0x00400046 // DDRC_RFSHTMG
  57. DATA 4 0x307a0490 0x00000001 // DDRC_PCTRL_0
  58. DATA 4 0x307A00D4 0x00690000 // DDRC_INIT1
  59. DATA 4 0x307A00D0 0x00020083 // DDRC_INIT0
  60. DATA 4 0x307A00DC 0x09300004 // DDRC_INIT3
  61. DATA 4 0x307A00E0 0x04080000 // DDRC_INIT4
  62. DATA 4 0x307A00E4 0x00100004 // DDRC_INIT5
  63. DATA 4 0x307A00F4 0x0000033F // DDRC_RANKCTL
  64. DATA 4 0x307A0100 0x090B1109 // DDRC_DRAMTMG0
  65. DATA 4 0x307A0104 0x0007020D // DDRC_DRAMTMG1
  66. DATA 4 0x307A0108 0x03040407 // DDRC_DRAMTMG2
  67. DATA 4 0x307A010C 0x00002006 // DDRC_DRAMTMG3
  68. DATA 4 0x307A0110 0x04020205 // DDRC_DRAMTMG4
  69. DATA 4 0x307A0114 0x03030202 // DDRC_DRAMTMG5
  70. DATA 4 0x307A0120 0x00000803 // DDRC_DRAMTMG8
  71. DATA 4 0x307A0180 0x00800020 // DDRC_ZQCTL0
  72. DATA 4 0x307A0190 0x02098204 // DDRC_DFITMG0
  73. DATA 4 0x307A0194 0x00030303 // DDRC_DFITMG1
  74. DATA 4 0x307A01A0 0x80400003 // DDRC_DFIUPD0
  75. DATA 4 0x307A01A4 0x00100020 // DDRC_DFIUPD1
  76. DATA 4 0x307A01A8 0x80100004 // DDRC_DFIUPD2
  77. DATA 4 0x307A0200 0x00000015 // DDRC_ADDRMAP0
  78. DATA 4 0x307A0204 0x00070707 // DDRC_ADDRMAP1
  79. DATA 4 0x307A0210 0x00000F0F // DDRC_ADDRMAP4
  80. DATA 4 0x307A0214 0x06060606 // DDRC_ADDRMAP5
  81. DATA 4 0x307A0218 0x0F060606 // DDRC_ADDRMAP6
  82. DATA 4 0x307A0240 0x06000604 // DDRC_ODTCFG
  83. DATA 4 0x307A0244 0x00000001 // DDRC_ODTMAP
  84. /* =============================================================================
  85. * PHY Control Register
  86. * =============================================================================
  87. */
  88. DATA 4 0x30391000 0x00000000 // deassert presetn
  89. DATA 4 0x30790000 0x17420F40 // DDR_PHY_PHY_CON0
  90. DATA 4 0x30790004 0x10210100 // DDR_PHY_PHY_CON1
  91. DATA 4 0x30790010 0x00060807 // DDR_PHY_PHY_CON4
  92. DATA 4 0x307900B0 0x1010007E // DDR_PHY_MDLL_CON0
  93. DATA 4 0x3079009C 0x00000D6E // DDR_PHY_DRVDS_CON0
  94. DATA 4 0x30790030 0x08080808 // DDR_PHY_OFFSET_WR_CON0
  95. DATA 4 0x30790020 0x08080808 // DDR_PHY_OFFSET_RD_CON0
  96. DATA 4 0x30790050 0x01000010 // DDR_PHY_OFFSETD_CON0
  97. DATA 4 0x30790050 0x00000010 // DDR_PHY_OFFSETD_CON0
  98. DATA 4 0x30790018 0x0000000F // DDR_PHY_LP_CON0
  99. DATA 4 0x307900C0 0x0E407304 // DDR_PHY_ZQ_CON0 - Start Manual ZQ
  100. DATA 4 0x307900C0 0x0E447304
  101. DATA 4 0x307900C0 0x0E447306
  102. DATA 4 0x307900C0 0x0E447304 // <= NOTE: Depending on JTAG device used, may need ~ 7 us pause at this point.
  103. DATA 4 0x307900C0 0x0E407304 // DDR_PHY_ZQ_CON0 - End Manual ZQ
  104. /* =============================================================================
  105. * Final Initialization start sequence
  106. * =============================================================================
  107. */
  108. DATA 4 0x30384130 0x00000000 // Disable Clock
  109. DATA 4 0x30340020 0x00000178 // IOMUX_GRP_GRP8 - Start input to PHY
  110. DATA 4 0x30384130 0x00000002 // Enable Clock
  111. /* <= NOTE: Depending on JTAG device used, may need ~ 250 us pause at this point. */