cpu.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Sascha Hauer, Pengutronix
  5. *
  6. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  7. */
  8. #include <bootm.h>
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <init.h>
  12. #include <log.h>
  13. #include <net.h>
  14. #include <netdev.h>
  15. #include <linux/errno.h>
  16. #include <asm/io.h>
  17. #include <asm/arch/imx-regs.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/arch/sys_proto.h>
  20. #include <asm/arch/crm_regs.h>
  21. #include <asm/mach-imx/boot_mode.h>
  22. #include <imx_thermal.h>
  23. #include <ipu_pixfmt.h>
  24. #include <thermal.h>
  25. #include <sata.h>
  26. #ifdef CONFIG_FSL_ESDHC_IMX
  27. #include <fsl_esdhc_imx.h>
  28. #endif
  29. static u32 reset_cause = -1;
  30. u32 get_imx_reset_cause(void)
  31. {
  32. struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  33. if (reset_cause == -1) {
  34. reset_cause = readl(&src_regs->srsr);
  35. /* preserve the value for U-Boot proper */
  36. #if !defined(CONFIG_SPL_BUILD)
  37. writel(reset_cause, &src_regs->srsr);
  38. #endif
  39. }
  40. return reset_cause;
  41. }
  42. #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
  43. static char *get_reset_cause(void)
  44. {
  45. switch (get_imx_reset_cause()) {
  46. case 0x00001:
  47. case 0x00011:
  48. return "POR";
  49. case 0x00004:
  50. return "CSU";
  51. case 0x00008:
  52. return "IPP USER";
  53. case 0x00010:
  54. #ifdef CONFIG_MX7
  55. return "WDOG1";
  56. #else
  57. return "WDOG";
  58. #endif
  59. case 0x00020:
  60. return "JTAG HIGH-Z";
  61. case 0x00040:
  62. return "JTAG SW";
  63. case 0x00080:
  64. return "WDOG3";
  65. #ifdef CONFIG_MX7
  66. case 0x00100:
  67. return "WDOG4";
  68. case 0x00200:
  69. return "TEMPSENSE";
  70. #elif defined(CONFIG_IMX8M)
  71. case 0x00100:
  72. return "WDOG2";
  73. case 0x00200:
  74. return "TEMPSENSE";
  75. #else
  76. case 0x00100:
  77. return "TEMPSENSE";
  78. case 0x10000:
  79. return "WARM BOOT";
  80. #endif
  81. default:
  82. return "unknown reset";
  83. }
  84. }
  85. #endif
  86. #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
  87. const char *get_imx_type(u32 imxtype)
  88. {
  89. switch (imxtype) {
  90. case MXC_CPU_IMX8MP:
  91. return "8MP[8]"; /* Quad-core version of the imx8mp */
  92. case MXC_CPU_IMX8MPD:
  93. return "8MP Dual[3]"; /* Dual-core version of the imx8mp */
  94. case MXC_CPU_IMX8MPL:
  95. return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */
  96. case MXC_CPU_IMX8MP7:
  97. return "8MP[7]"; /* Quad-core version of the imx8mp, VPU fused */
  98. case MXC_CPU_IMX8MP6:
  99. return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */
  100. case MXC_CPU_IMX8MP5:
  101. return "8MP[5]"; /* Quad-core version of the imx8mp, ISP fused */
  102. case MXC_CPU_IMX8MN:
  103. return "8MNano Quad"; /* Quad-core version */
  104. case MXC_CPU_IMX8MND:
  105. return "8MNano Dual"; /* Dual-core version */
  106. case MXC_CPU_IMX8MNS:
  107. return "8MNano Solo"; /* Single-core version */
  108. case MXC_CPU_IMX8MNL:
  109. return "8MNano QuadLite"; /* Quad-core Lite version */
  110. case MXC_CPU_IMX8MNDL:
  111. return "8MNano DualLite"; /* Dual-core Lite version */
  112. case MXC_CPU_IMX8MNSL:
  113. return "8MNano SoloLite"; /* Single-core Lite version */
  114. case MXC_CPU_IMX8MM:
  115. return "8MMQ"; /* Quad-core version of the imx8mm */
  116. case MXC_CPU_IMX8MML:
  117. return "8MMQL"; /* Quad-core Lite version of the imx8mm */
  118. case MXC_CPU_IMX8MMD:
  119. return "8MMD"; /* Dual-core version of the imx8mm */
  120. case MXC_CPU_IMX8MMDL:
  121. return "8MMDL"; /* Dual-core Lite version of the imx8mm */
  122. case MXC_CPU_IMX8MMS:
  123. return "8MMS"; /* Single-core version of the imx8mm */
  124. case MXC_CPU_IMX8MMSL:
  125. return "8MMSL"; /* Single-core Lite version of the imx8mm */
  126. case MXC_CPU_IMX8MQ:
  127. return "8MQ"; /* Quad-core version of the imx8mq */
  128. case MXC_CPU_IMX8MQL:
  129. return "8MQLite"; /* Quad-core Lite version of the imx8mq */
  130. case MXC_CPU_IMX8MD:
  131. return "8MD"; /* Dual-core version of the imx8mq */
  132. case MXC_CPU_MX7S:
  133. return "7S"; /* Single-core version of the mx7 */
  134. case MXC_CPU_MX7D:
  135. return "7D"; /* Dual-core version of the mx7 */
  136. case MXC_CPU_MX6QP:
  137. return "6QP"; /* Quad-Plus version of the mx6 */
  138. case MXC_CPU_MX6DP:
  139. return "6DP"; /* Dual-Plus version of the mx6 */
  140. case MXC_CPU_MX6Q:
  141. return "6Q"; /* Quad-core version of the mx6 */
  142. case MXC_CPU_MX6D:
  143. return "6D"; /* Dual-core version of the mx6 */
  144. case MXC_CPU_MX6DL:
  145. return "6DL"; /* Dual Lite version of the mx6 */
  146. case MXC_CPU_MX6SOLO:
  147. return "6SOLO"; /* Solo version of the mx6 */
  148. case MXC_CPU_MX6SL:
  149. return "6SL"; /* Solo-Lite version of the mx6 */
  150. case MXC_CPU_MX6SLL:
  151. return "6SLL"; /* SLL version of the mx6 */
  152. case MXC_CPU_MX6SX:
  153. return "6SX"; /* SoloX version of the mx6 */
  154. case MXC_CPU_MX6UL:
  155. return "6UL"; /* Ultra-Lite version of the mx6 */
  156. case MXC_CPU_MX6ULL:
  157. return "6ULL"; /* ULL version of the mx6 */
  158. case MXC_CPU_MX6ULZ:
  159. return "6ULZ"; /* ULZ version of the mx6 */
  160. case MXC_CPU_MX51:
  161. return "51";
  162. case MXC_CPU_MX53:
  163. return "53";
  164. default:
  165. return "??";
  166. }
  167. }
  168. int print_cpuinfo(void)
  169. {
  170. u32 cpurev;
  171. __maybe_unused u32 max_freq;
  172. cpurev = get_cpu_rev();
  173. #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
  174. struct udevice *thermal_dev;
  175. int cpu_tmp, minc, maxc, ret;
  176. printf("CPU: Freescale i.MX%s rev%d.%d",
  177. get_imx_type((cpurev & 0x1FF000) >> 12),
  178. (cpurev & 0x000F0) >> 4,
  179. (cpurev & 0x0000F) >> 0);
  180. max_freq = get_cpu_speed_grade_hz();
  181. if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
  182. printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
  183. } else {
  184. printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
  185. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  186. }
  187. #else
  188. printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
  189. get_imx_type((cpurev & 0x1FF000) >> 12),
  190. (cpurev & 0x000F0) >> 4,
  191. (cpurev & 0x0000F) >> 0,
  192. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  193. #endif
  194. #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU)
  195. puts("CPU: ");
  196. switch (get_cpu_temp_grade(&minc, &maxc)) {
  197. case TEMP_AUTOMOTIVE:
  198. puts("Automotive temperature grade ");
  199. break;
  200. case TEMP_INDUSTRIAL:
  201. puts("Industrial temperature grade ");
  202. break;
  203. case TEMP_EXTCOMMERCIAL:
  204. puts("Extended Commercial temperature grade ");
  205. break;
  206. default:
  207. puts("Commercial temperature grade ");
  208. break;
  209. }
  210. printf("(%dC to %dC)", minc, maxc);
  211. ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
  212. if (!ret) {
  213. ret = thermal_get_temp(thermal_dev, &cpu_tmp);
  214. if (!ret)
  215. printf(" at %dC\n", cpu_tmp);
  216. else
  217. debug(" - invalid sensor data\n");
  218. } else {
  219. debug(" - invalid sensor device\n");
  220. }
  221. #endif
  222. printf("Reset cause: %s\n", get_reset_cause());
  223. return 0;
  224. }
  225. #endif
  226. int cpu_eth_init(struct bd_info *bis)
  227. {
  228. int rc = -ENODEV;
  229. #if defined(CONFIG_FEC_MXC)
  230. rc = fecmxc_initialize(bis);
  231. #endif
  232. return rc;
  233. }
  234. #ifdef CONFIG_FSL_ESDHC_IMX
  235. /*
  236. * Initializes on-chip MMC controllers.
  237. * to override, implement board_mmc_init()
  238. */
  239. int cpu_mmc_init(struct bd_info *bis)
  240. {
  241. return fsl_esdhc_mmc_init(bis);
  242. }
  243. #endif
  244. #if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
  245. u32 get_ahb_clk(void)
  246. {
  247. struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  248. u32 reg, ahb_podf;
  249. reg = __raw_readl(&imx_ccm->cbcdr);
  250. reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
  251. ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
  252. return get_periph_clk() / (ahb_podf + 1);
  253. }
  254. #endif
  255. void arch_preboot_os(void)
  256. {
  257. #if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
  258. imx_pcie_remove();
  259. #endif
  260. #if defined(CONFIG_SATA)
  261. if (!is_mx6sdl()) {
  262. sata_remove(0);
  263. #if defined(CONFIG_MX6)
  264. disable_sata_clock();
  265. #endif
  266. }
  267. #endif
  268. #if defined(CONFIG_VIDEO_IPUV3)
  269. /* disable video before launching O/S */
  270. ipuv3_fb_shutdown();
  271. #endif
  272. #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
  273. lcdif_power_down();
  274. #endif
  275. }
  276. #ifndef CONFIG_IMX8M
  277. void set_chipselect_size(int const cs_size)
  278. {
  279. unsigned int reg;
  280. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  281. reg = readl(&iomuxc_regs->gpr[1]);
  282. switch (cs_size) {
  283. case CS0_128:
  284. reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
  285. reg |= 0x5;
  286. break;
  287. case CS0_64M_CS1_64M:
  288. reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
  289. reg |= 0x1B;
  290. break;
  291. case CS0_64M_CS1_32M_CS2_32M:
  292. reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
  293. reg |= 0x4B;
  294. break;
  295. case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
  296. reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
  297. reg |= 0x249;
  298. break;
  299. default:
  300. printf("Unknown chip select size: %d\n", cs_size);
  301. break;
  302. }
  303. writel(reg, &iomuxc_regs->gpr[1]);
  304. }
  305. #endif
  306. #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
  307. /*
  308. * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
  309. * defines a 2-bit SPEED_GRADING
  310. */
  311. #define OCOTP_TESTER3_SPEED_SHIFT 8
  312. enum cpu_speed {
  313. OCOTP_TESTER3_SPEED_GRADE0,
  314. OCOTP_TESTER3_SPEED_GRADE1,
  315. OCOTP_TESTER3_SPEED_GRADE2,
  316. OCOTP_TESTER3_SPEED_GRADE3,
  317. OCOTP_TESTER3_SPEED_GRADE4,
  318. };
  319. u32 get_cpu_speed_grade_hz(void)
  320. {
  321. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  322. struct fuse_bank *bank = &ocotp->bank[1];
  323. struct fuse_bank1_regs *fuse =
  324. (struct fuse_bank1_regs *)bank->fuse_regs;
  325. uint32_t val;
  326. val = readl(&fuse->tester3);
  327. val >>= OCOTP_TESTER3_SPEED_SHIFT;
  328. if (is_imx8mn() || is_imx8mp()) {
  329. val &= 0xf;
  330. return 2300000000 - val * 100000000;
  331. }
  332. if (is_imx8mm())
  333. val &= 0x7;
  334. else
  335. val &= 0x3;
  336. switch(val) {
  337. case OCOTP_TESTER3_SPEED_GRADE0:
  338. return 800000000;
  339. case OCOTP_TESTER3_SPEED_GRADE1:
  340. return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000));
  341. case OCOTP_TESTER3_SPEED_GRADE2:
  342. return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000));
  343. case OCOTP_TESTER3_SPEED_GRADE3:
  344. return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000));
  345. case OCOTP_TESTER3_SPEED_GRADE4:
  346. return 2000000000;
  347. }
  348. return 0;
  349. }
  350. /*
  351. * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
  352. * defines a 2-bit SPEED_GRADING
  353. */
  354. #define OCOTP_TESTER3_TEMP_SHIFT 6
  355. u32 get_cpu_temp_grade(int *minc, int *maxc)
  356. {
  357. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  358. struct fuse_bank *bank = &ocotp->bank[1];
  359. struct fuse_bank1_regs *fuse =
  360. (struct fuse_bank1_regs *)bank->fuse_regs;
  361. uint32_t val;
  362. val = readl(&fuse->tester3);
  363. val >>= OCOTP_TESTER3_TEMP_SHIFT;
  364. val &= 0x3;
  365. if (minc && maxc) {
  366. if (val == TEMP_AUTOMOTIVE) {
  367. *minc = -40;
  368. *maxc = 125;
  369. } else if (val == TEMP_INDUSTRIAL) {
  370. *minc = -40;
  371. *maxc = 105;
  372. } else if (val == TEMP_EXTCOMMERCIAL) {
  373. *minc = -20;
  374. *maxc = 105;
  375. } else {
  376. *minc = 0;
  377. *maxc = 95;
  378. }
  379. }
  380. return val;
  381. }
  382. #endif
  383. #if defined(CONFIG_MX7) || defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM)
  384. enum boot_device get_boot_device(void)
  385. {
  386. struct bootrom_sw_info **p =
  387. (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
  388. enum boot_device boot_dev = SD1_BOOT;
  389. u8 boot_type = (*p)->boot_dev_type;
  390. u8 boot_instance = (*p)->boot_dev_instance;
  391. switch (boot_type) {
  392. case BOOT_TYPE_SD:
  393. boot_dev = boot_instance + SD1_BOOT;
  394. break;
  395. case BOOT_TYPE_MMC:
  396. boot_dev = boot_instance + MMC1_BOOT;
  397. break;
  398. case BOOT_TYPE_NAND:
  399. boot_dev = NAND_BOOT;
  400. break;
  401. case BOOT_TYPE_QSPI:
  402. boot_dev = QSPI_BOOT;
  403. break;
  404. case BOOT_TYPE_WEIM:
  405. boot_dev = WEIM_NOR_BOOT;
  406. break;
  407. case BOOT_TYPE_SPINOR:
  408. boot_dev = SPI_NOR_BOOT;
  409. break;
  410. #ifdef CONFIG_IMX8M
  411. case BOOT_TYPE_USB:
  412. boot_dev = USB_BOOT;
  413. break;
  414. #endif
  415. default:
  416. break;
  417. }
  418. return boot_dev;
  419. }
  420. #endif
  421. #ifdef CONFIG_NXP_BOARD_REVISION
  422. int nxp_board_rev(void)
  423. {
  424. /*
  425. * Get Board ID information from OCOTP_GP1[15:8]
  426. * RevA: 0x1
  427. * RevB: 0x2
  428. * RevC: 0x3
  429. */
  430. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  431. struct fuse_bank *bank = &ocotp->bank[4];
  432. struct fuse_bank4_regs *fuse =
  433. (struct fuse_bank4_regs *)bank->fuse_regs;
  434. return (readl(&fuse->gp1) >> 8 & 0x0F);
  435. }
  436. char nxp_board_rev_string(void)
  437. {
  438. const char *rev = "A";
  439. return (*rev + nxp_board_rev() - 1);
  440. }
  441. #endif