quark.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <mmc.h>
  8. #include <asm/cache.h>
  9. #include <asm/io.h>
  10. #include <asm/ioapic.h>
  11. #include <asm/irq.h>
  12. #include <asm/mrccache.h>
  13. #include <asm/mtrr.h>
  14. #include <asm/pci.h>
  15. #include <asm/post.h>
  16. #include <asm/arch/device.h>
  17. #include <asm/arch/msg_port.h>
  18. #include <asm/arch/quark.h>
  19. static void quark_setup_mtrr(void)
  20. {
  21. u32 base, mask;
  22. int i;
  23. disable_caches();
  24. /* mark the VGA RAM area as uncacheable */
  25. msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_A0000,
  26. MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
  27. msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_B0000,
  28. MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
  29. /* mark other fixed range areas as cacheable */
  30. msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_00000,
  31. MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
  32. msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_40000,
  33. MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
  34. msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_80000,
  35. MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
  36. msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_90000,
  37. MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
  38. for (i = MTRR_FIX_4K_C0000; i <= MTRR_FIX_4K_FC000; i++)
  39. msg_port_write(MSG_PORT_HOST_BRIDGE, i,
  40. MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
  41. /* variable range MTRR#0: ROM area */
  42. mask = ~(CONFIG_SYS_MONITOR_LEN - 1);
  43. base = CONFIG_SYS_TEXT_BASE & mask;
  44. msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ROM),
  45. base | MTRR_TYPE_WRBACK);
  46. msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ROM),
  47. mask | MTRR_PHYS_MASK_VALID);
  48. /* variable range MTRR#1: eSRAM area */
  49. mask = ~(ESRAM_SIZE - 1);
  50. base = CONFIG_ESRAM_BASE & mask;
  51. msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ESRAM),
  52. base | MTRR_TYPE_WRBACK);
  53. msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ESRAM),
  54. mask | MTRR_PHYS_MASK_VALID);
  55. /* enable both variable and fixed range MTRRs */
  56. msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_DEF_TYPE,
  57. MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN);
  58. enable_caches();
  59. }
  60. static void quark_setup_bars(void)
  61. {
  62. /* GPIO - D31:F0:R44h */
  63. qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA,
  64. CONFIG_GPIO_BASE | IO_BAR_EN);
  65. /* ACPI PM1 Block - D31:F0:R48h */
  66. qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK,
  67. CONFIG_ACPI_PM1_BASE | IO_BAR_EN);
  68. /* GPE0 - D31:F0:R4Ch */
  69. qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK,
  70. CONFIG_ACPI_GPE0_BASE | IO_BAR_EN);
  71. /* WDT - D31:F0:R84h */
  72. qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA,
  73. CONFIG_WDT_BASE | IO_BAR_EN);
  74. /* RCBA - D31:F0:RF0h */
  75. qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA,
  76. CONFIG_RCBA_BASE | MEM_BAR_EN);
  77. /* ACPI P Block - Msg Port 04:R70h */
  78. msg_port_write(MSG_PORT_RMU, PBLK_BA,
  79. CONFIG_ACPI_PBLK_BASE | IO_BAR_EN);
  80. /* SPI DMA - Msg Port 04:R7Ah */
  81. msg_port_write(MSG_PORT_RMU, SPI_DMA_BA,
  82. CONFIG_SPI_DMA_BASE | IO_BAR_EN);
  83. /* PCIe ECAM */
  84. msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL,
  85. CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
  86. msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG,
  87. CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
  88. }
  89. static void quark_pcie_early_init(void)
  90. {
  91. /*
  92. * Step1: Assert PCIe signal PERST#
  93. *
  94. * The CPU interface to the PERST# signal is platform dependent.
  95. * Call the board-specific codes to perform this task.
  96. */
  97. board_assert_perst();
  98. /* Step2: PHY common lane reset */
  99. msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_PHY_LANE_RST);
  100. /* wait 1 ms for PHY common lane reset */
  101. mdelay(1);
  102. /* Step3: PHY sideband interface reset and controller main reset */
  103. msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG,
  104. PCIE_PHY_SB_RST | PCIE_CTLR_MAIN_RST);
  105. /* wait 80ms for PLL to lock */
  106. mdelay(80);
  107. /* Step4: Controller sideband interface reset */
  108. msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_SB_RST);
  109. /* wait 20ms for controller sideband interface reset */
  110. mdelay(20);
  111. /* Step5: De-assert PERST# */
  112. board_deassert_perst();
  113. /* Step6: Controller primary interface reset */
  114. msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_PRI_RST);
  115. /* Mixer Load Lane 0 */
  116. msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0,
  117. (1 << 6) | (1 << 7));
  118. /* Mixer Load Lane 1 */
  119. msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1,
  120. (1 << 6) | (1 << 7));
  121. }
  122. static void quark_usb_early_init(void)
  123. {
  124. /* The sequence below comes from Quark firmware writer guide */
  125. msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT,
  126. 1 << 1, (1 << 6) | (1 << 7));
  127. msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_COMPBG,
  128. (1 << 8) | (1 << 9), (1 << 7) | (1 << 10));
  129. msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29);
  130. msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL1, 1 << 1);
  131. msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_PLL1,
  132. (1 << 3) | (1 << 4) | (1 << 5), 1 << 6);
  133. msg_port_alt_clrbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29);
  134. msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 24);
  135. }
  136. static void quark_thermal_early_init(void)
  137. {
  138. /* The sequence below comes from Quark firmware writer guide */
  139. /* thermal sensor mode config */
  140. msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1,
  141. (1 << 3) | (1 << 4) | (1 << 5), 1 << 5);
  142. msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1,
  143. (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) |
  144. (1 << 12), 1 << 9);
  145. msg_port_alt_setbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 14);
  146. msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 17);
  147. msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 18);
  148. msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG2, 0xffff, 0x011f);
  149. msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff, 0x17);
  150. msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3,
  151. (1 << 8) | (1 << 9), 1 << 8);
  152. msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff000000);
  153. msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG4,
  154. 0x7ff800, 0xc8 << 11);
  155. /* thermal monitor catastrophic trip set point (105 celsius) */
  156. msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff, 155);
  157. /* thermal monitor catastrophic trip clear point (0 celsius) */
  158. msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff0000, 50 << 16);
  159. /* take thermal sensor out of reset */
  160. msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG4, 1 << 0);
  161. /* enable thermal monitor */
  162. msg_port_setbits(MSG_PORT_RMU, TS_MODE, 1 << 15);
  163. /* lock all thermal configuration */
  164. msg_port_setbits(MSG_PORT_RMU, RMU_CTRL, (1 << 5) | (1 << 6));
  165. }
  166. static void quark_enable_legacy_seg(void)
  167. {
  168. msg_port_setbits(MSG_PORT_HOST_BRIDGE, HMISC2,
  169. HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB);
  170. }
  171. int arch_cpu_init(void)
  172. {
  173. int ret;
  174. post_code(POST_CPU_INIT);
  175. ret = x86_cpu_init_f();
  176. if (ret)
  177. return ret;
  178. /*
  179. * Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs
  180. * are accessed indirectly via the message port and not the traditional
  181. * MSR mechanism. Only UC, WT and WB cache types are supported.
  182. */
  183. quark_setup_mtrr();
  184. /*
  185. * Quark SoC has some non-standard BARs (excluding PCI standard BARs)
  186. * which need be initialized with suggested values
  187. */
  188. quark_setup_bars();
  189. /* Initialize USB2 PHY */
  190. quark_usb_early_init();
  191. /* Initialize thermal sensor */
  192. quark_thermal_early_init();
  193. /* Turn on legacy segments (A/B/E/F) decode to system RAM */
  194. quark_enable_legacy_seg();
  195. return 0;
  196. }
  197. int arch_cpu_init_dm(void)
  198. {
  199. /*
  200. * Initialize PCIe controller
  201. *
  202. * Quark SoC holds the PCIe controller in reset following a power on.
  203. * U-Boot needs to release the PCIe controller from reset. The PCIe
  204. * controller (D23:F0/F1) will not be visible in PCI configuration
  205. * space and any access to its PCI configuration registers will cause
  206. * system hang while it is held in reset.
  207. */
  208. quark_pcie_early_init();
  209. return 0;
  210. }
  211. int checkcpu(void)
  212. {
  213. return 0;
  214. }
  215. int print_cpuinfo(void)
  216. {
  217. post_code(POST_CPU_INFO);
  218. return default_print_cpuinfo();
  219. }
  220. static void quark_pcie_init(void)
  221. {
  222. u32 val;
  223. /* PCIe upstream non-posted & posted request size */
  224. qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_CCFG,
  225. CCFG_UPRS | CCFG_UNRS);
  226. qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_CCFG,
  227. CCFG_UPRS | CCFG_UNRS);
  228. /* PCIe packet fast transmit mode (IPF) */
  229. qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MPC2, MPC2_IPF);
  230. qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MPC2, MPC2_IPF);
  231. /* PCIe message bus idle counter (SBIC) */
  232. qrk_pci_read_config_dword(QUARK_PCIE0, PCIE_RP_MBC, &val);
  233. val |= MBC_SBIC;
  234. qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MBC, val);
  235. qrk_pci_read_config_dword(QUARK_PCIE1, PCIE_RP_MBC, &val);
  236. val |= MBC_SBIC;
  237. qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MBC, val);
  238. }
  239. static void quark_usb_init(void)
  240. {
  241. u32 bar;
  242. /* Change USB EHCI packet buffer OUT/IN threshold */
  243. qrk_pci_read_config_dword(QUARK_USB_EHCI, PCI_BASE_ADDRESS_0, &bar);
  244. writel((0x7f << 16) | 0x7f, bar + EHCI_INSNREG01);
  245. /* Disable USB device interrupts */
  246. qrk_pci_read_config_dword(QUARK_USB_DEVICE, PCI_BASE_ADDRESS_0, &bar);
  247. writel(0x7f, bar + USBD_INT_MASK);
  248. writel((0xf << 16) | 0xf, bar + USBD_EP_INT_MASK);
  249. writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS);
  250. }
  251. static void quark_irq_init(void)
  252. {
  253. struct quark_rcba *rcba;
  254. u32 base;
  255. qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
  256. base &= ~MEM_BAR_EN;
  257. rcba = (struct quark_rcba *)base;
  258. /*
  259. * Route Quark PCI device interrupt pin to PIRQ
  260. *
  261. * Route device#23's INTA/B/C/D to PIRQA/B/C/D
  262. * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H
  263. */
  264. writew(PIRQC, &rcba->rmu_ir);
  265. writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12),
  266. &rcba->d23_ir);
  267. writew(PIRQD, &rcba->core_ir);
  268. writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12),
  269. &rcba->d20d21_ir);
  270. }
  271. int arch_early_init_r(void)
  272. {
  273. quark_pcie_init();
  274. quark_usb_init();
  275. quark_irq_init();
  276. return 0;
  277. }
  278. int arch_misc_init(void)
  279. {
  280. #ifdef CONFIG_ENABLE_MRC_CACHE
  281. /*
  282. * We intend not to check any return value here, as even MRC cache
  283. * is not saved successfully, it is not a severe error that will
  284. * prevent system from continuing to boot.
  285. */
  286. mrccache_save();
  287. #endif
  288. /* Assign a unique I/O APIC ID */
  289. io_apic_set_id(1);
  290. return 0;
  291. }
  292. void board_final_cleanup(void)
  293. {
  294. struct quark_rcba *rcba;
  295. u32 base, val;
  296. qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
  297. base &= ~MEM_BAR_EN;
  298. rcba = (struct quark_rcba *)base;
  299. /* Initialize 'Component ID' to zero */
  300. val = readl(&rcba->esd);
  301. val &= ~0xff0000;
  302. writel(val, &rcba->esd);
  303. /* Lock HMBOUND for security */
  304. msg_port_setbits(MSG_PORT_HOST_BRIDGE, HM_BOUND, HM_BOUND_LOCK);
  305. return;
  306. }