clk-provider.h 5.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2019 DENX Software Engineering
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  5. *
  6. * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
  7. * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
  8. */
  9. #ifndef __LINUX_CLK_PROVIDER_H
  10. #define __LINUX_CLK_PROVIDER_H
  11. #include <dm.h>
  12. #include <linux/bitops.h>
  13. #include <linux/err.h>
  14. #include <clk-uclass.h>
  15. static inline void clk_dm(ulong id, struct clk *clk)
  16. {
  17. if (!IS_ERR(clk))
  18. clk->id = id;
  19. }
  20. /*
  21. * flags used across common struct clk. these flags should only affect the
  22. * top-level framework. custom flags for dealing with hardware specifics
  23. * belong in struct clk_foo
  24. *
  25. * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
  26. */
  27. #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
  28. #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
  29. #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
  30. #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
  31. /* unused */
  32. #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
  33. #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
  34. #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
  35. #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
  36. #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
  37. #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
  38. #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
  39. /* parents need enable during gate/ungate, set rate and re-parent */
  40. #define CLK_OPS_PARENT_ENABLE BIT(12)
  41. /* duty cycle call may be forwarded to the parent clock */
  42. #define CLK_DUTY_CYCLE_PARENT BIT(13)
  43. #define CLK_MUX_INDEX_ONE BIT(0)
  44. #define CLK_MUX_INDEX_BIT BIT(1)
  45. #define CLK_MUX_HIWORD_MASK BIT(2)
  46. #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
  47. #define CLK_MUX_ROUND_CLOSEST BIT(4)
  48. struct clk_mux {
  49. struct clk clk;
  50. void __iomem *reg;
  51. u32 *table;
  52. u32 mask;
  53. u8 shift;
  54. u8 flags;
  55. /*
  56. * Fields from struct clk_init_data - this struct has been
  57. * omitted to avoid too deep level of CCF for bootloader
  58. */
  59. const char * const *parent_names;
  60. u8 num_parents;
  61. #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
  62. u32 io_mux_val;
  63. #endif
  64. };
  65. #define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
  66. extern const struct clk_ops clk_mux_ops;
  67. u8 clk_mux_get_parent(struct clk *clk);
  68. struct clk_gate {
  69. struct clk clk;
  70. void __iomem *reg;
  71. u8 bit_idx;
  72. u8 flags;
  73. #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
  74. u32 io_gate_val;
  75. #endif
  76. };
  77. #define to_clk_gate(_clk) container_of(_clk, struct clk_gate, clk)
  78. #define CLK_GATE_SET_TO_DISABLE BIT(0)
  79. #define CLK_GATE_HIWORD_MASK BIT(1)
  80. extern const struct clk_ops clk_gate_ops;
  81. struct clk *clk_register_gate(struct device *dev, const char *name,
  82. const char *parent_name, unsigned long flags,
  83. void __iomem *reg, u8 bit_idx,
  84. u8 clk_gate_flags, spinlock_t *lock);
  85. struct clk_div_table {
  86. unsigned int val;
  87. unsigned int div;
  88. };
  89. struct clk_divider {
  90. struct clk clk;
  91. void __iomem *reg;
  92. u8 shift;
  93. u8 width;
  94. u8 flags;
  95. const struct clk_div_table *table;
  96. #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
  97. u32 io_divider_val;
  98. #endif
  99. };
  100. #define clk_div_mask(width) ((1 << (width)) - 1)
  101. #define to_clk_divider(_clk) container_of(_clk, struct clk_divider, clk)
  102. #define CLK_DIVIDER_ONE_BASED BIT(0)
  103. #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
  104. #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
  105. #define CLK_DIVIDER_HIWORD_MASK BIT(3)
  106. #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
  107. #define CLK_DIVIDER_READ_ONLY BIT(5)
  108. #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
  109. extern const struct clk_ops clk_divider_ops;
  110. unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
  111. unsigned int val,
  112. const struct clk_div_table *table,
  113. unsigned long flags, unsigned long width);
  114. struct clk_fixed_factor {
  115. struct clk clk;
  116. unsigned int mult;
  117. unsigned int div;
  118. };
  119. #define to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\
  120. clk)
  121. struct clk_fixed_rate {
  122. struct clk clk;
  123. unsigned long fixed_rate;
  124. };
  125. #define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_platdata(dev))
  126. struct clk_composite {
  127. struct clk clk;
  128. struct clk_ops ops;
  129. struct clk *mux;
  130. struct clk *rate;
  131. struct clk *gate;
  132. const struct clk_ops *mux_ops;
  133. const struct clk_ops *rate_ops;
  134. const struct clk_ops *gate_ops;
  135. };
  136. #define to_clk_composite(_clk) container_of(_clk, struct clk_composite, clk)
  137. struct clk *clk_register_composite(struct device *dev, const char *name,
  138. const char * const *parent_names, int num_parents,
  139. struct clk *mux_clk, const struct clk_ops *mux_ops,
  140. struct clk *rate_clk, const struct clk_ops *rate_ops,
  141. struct clk *gate_clk, const struct clk_ops *gate_ops,
  142. unsigned long flags);
  143. int clk_register(struct clk *clk, const char *drv_name, const char *name,
  144. const char *parent_name);
  145. struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
  146. const char *parent_name, unsigned long flags,
  147. unsigned int mult, unsigned int div);
  148. struct clk *clk_register_divider(struct device *dev, const char *name,
  149. const char *parent_name, unsigned long flags,
  150. void __iomem *reg, u8 shift, u8 width,
  151. u8 clk_divider_flags);
  152. struct clk *clk_register_mux(struct device *dev, const char *name,
  153. const char * const *parent_names, u8 num_parents,
  154. unsigned long flags,
  155. void __iomem *reg, u8 shift, u8 width,
  156. u8 clk_mux_flags);
  157. const char *clk_hw_get_name(const struct clk *hw);
  158. ulong clk_generic_get_rate(struct clk *clk);
  159. static inline struct clk *dev_get_clk_ptr(struct udevice *dev)
  160. {
  161. return (struct clk *)dev_get_uclass_priv(dev);
  162. }
  163. #endif /* __LINUX_CLK_PROVIDER_H */