clk-mtk.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MediaTek common clock driver
  4. *
  5. * Copyright (C) 2018 MediaTek Inc.
  6. * Author: Ryder Lee <ryder.lee@mediatek.com>
  7. */
  8. #include <common.h>
  9. #include <clk-uclass.h>
  10. #include <div64.h>
  11. #include <dm.h>
  12. #include <asm/io.h>
  13. #include "clk-mtk.h"
  14. #define REG_CON0 0
  15. #define REG_CON1 4
  16. #define CON0_BASE_EN BIT(0)
  17. #define CON0_PWR_ON BIT(0)
  18. #define CON0_ISO_EN BIT(1)
  19. #define CON1_PCW_CHG BIT(31)
  20. #define POSTDIV_MASK 0x7
  21. #define INTEGER_BITS 7
  22. /* scpsys clock off control */
  23. #define CLK_SCP_CFG0 0x200
  24. #define CLK_SCP_CFG1 0x204
  25. #define SCP_ARMCK_OFF_EN GENMASK(9, 0)
  26. #define SCP_AXICK_DCM_DIS_EN BIT(0)
  27. #define SCP_AXICK_26M_SEL_EN BIT(4)
  28. /* shared functions */
  29. /*
  30. * In case the rate change propagation to parent clocks is undesirable,
  31. * this function is recursively called to find the parent to calculate
  32. * the accurate frequency.
  33. */
  34. static ulong mtk_clk_find_parent_rate(struct clk *clk, int id,
  35. const struct driver *drv)
  36. {
  37. struct clk parent = { .id = id, };
  38. if (drv) {
  39. struct udevice *dev;
  40. if (uclass_get_device_by_driver(UCLASS_CLK, drv, &dev))
  41. return -ENODEV;
  42. parent.dev = dev;
  43. } else {
  44. parent.dev = clk->dev;
  45. }
  46. return clk_get_rate(&parent);
  47. }
  48. static int mtk_clk_mux_set_parent(void __iomem *base, u32 parent,
  49. const struct mtk_composite *mux)
  50. {
  51. u32 val, index = 0;
  52. while (mux->parent[index] != parent)
  53. if (++index == mux->num_parents)
  54. return -EINVAL;
  55. if (mux->flags & CLK_MUX_SETCLR_UPD) {
  56. val = (mux->mux_mask << mux->mux_shift);
  57. writel(val, base + mux->mux_clr_reg);
  58. val = (index << mux->mux_shift);
  59. writel(val, base + mux->mux_set_reg);
  60. if (mux->upd_shift >= 0)
  61. writel(BIT(mux->upd_shift), base + mux->upd_reg);
  62. } else {
  63. /* switch mux to a select parent */
  64. val = readl(base + mux->mux_reg);
  65. val &= ~(mux->mux_mask << mux->mux_shift);
  66. val |= index << mux->mux_shift;
  67. writel(val, base + mux->mux_reg);
  68. }
  69. return 0;
  70. }
  71. /* apmixedsys functions */
  72. static unsigned long __mtk_pll_recalc_rate(const struct mtk_pll_data *pll,
  73. u32 fin, u32 pcw, int postdiv)
  74. {
  75. int pcwbits = pll->pcwbits;
  76. int pcwfbits;
  77. int ibits;
  78. u64 vco;
  79. u8 c = 0;
  80. /* The fractional part of the PLL divider. */
  81. ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS;
  82. pcwfbits = pcwbits > ibits ? pcwbits - ibits : 0;
  83. vco = (u64)fin * pcw;
  84. if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))
  85. c = 1;
  86. vco >>= pcwfbits;
  87. if (c)
  88. vco++;
  89. return ((unsigned long)vco + postdiv - 1) / postdiv;
  90. }
  91. /**
  92. * MediaTek PLLs are configured through their pcw value. The pcw value
  93. * describes a divider in the PLL feedback loop which consists of 7 bits
  94. * for the integer part and the remaining bits (if present) for the
  95. * fractional part. Also they have a 3 bit power-of-two post divider.
  96. */
  97. static void mtk_pll_set_rate_regs(struct clk *clk, u32 pcw, int postdiv)
  98. {
  99. struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  100. const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
  101. u32 val, chg;
  102. /* set postdiv */
  103. val = readl(priv->base + pll->pd_reg);
  104. val &= ~(POSTDIV_MASK << pll->pd_shift);
  105. val |= (ffs(postdiv) - 1) << pll->pd_shift;
  106. /* postdiv and pcw need to set at the same time if on same register */
  107. if (pll->pd_reg != pll->pcw_reg) {
  108. writel(val, priv->base + pll->pd_reg);
  109. val = readl(priv->base + pll->pcw_reg);
  110. }
  111. /* set pcw */
  112. val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift);
  113. val |= pcw << pll->pcw_shift;
  114. if (pll->pcw_chg_reg) {
  115. chg = readl(priv->base + pll->pcw_chg_reg);
  116. chg |= CON1_PCW_CHG;
  117. writel(val, priv->base + pll->pcw_reg);
  118. writel(chg, priv->base + pll->pcw_chg_reg);
  119. } else {
  120. val |= CON1_PCW_CHG;
  121. writel(val, priv->base + pll->pcw_reg);
  122. }
  123. udelay(20);
  124. }
  125. /**
  126. * mtk_pll_calc_values - calculate good values for a given input frequency.
  127. * @clk: The clk
  128. * @pcw: The pcw value (output)
  129. * @postdiv: The post divider (output)
  130. * @freq: The desired target frequency
  131. */
  132. static void mtk_pll_calc_values(struct clk *clk, u32 *pcw, u32 *postdiv,
  133. u32 freq)
  134. {
  135. struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  136. const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
  137. unsigned long fmin = pll->fmin ? pll->fmin : 1000 * MHZ;
  138. u64 _pcw;
  139. int ibits;
  140. u32 val;
  141. if (freq > pll->fmax)
  142. freq = pll->fmax;
  143. for (val = 0; val < 5; val++) {
  144. *postdiv = 1 << val;
  145. if ((u64)freq * *postdiv >= fmin)
  146. break;
  147. }
  148. /* _pcw = freq * postdiv / xtal_rate * 2^pcwfbits */
  149. ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS;
  150. _pcw = ((u64)freq << val) << (pll->pcwbits - ibits);
  151. do_div(_pcw, priv->tree->xtal2_rate);
  152. *pcw = (u32)_pcw;
  153. }
  154. static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate)
  155. {
  156. u32 pcw = 0;
  157. u32 postdiv;
  158. mtk_pll_calc_values(clk, &pcw, &postdiv, rate);
  159. mtk_pll_set_rate_regs(clk, pcw, postdiv);
  160. return 0;
  161. }
  162. static ulong mtk_apmixedsys_get_rate(struct clk *clk)
  163. {
  164. struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  165. const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
  166. u32 postdiv;
  167. u32 pcw;
  168. postdiv = (readl(priv->base + pll->pd_reg) >> pll->pd_shift) &
  169. POSTDIV_MASK;
  170. postdiv = 1 << postdiv;
  171. pcw = readl(priv->base + pll->pcw_reg) >> pll->pcw_shift;
  172. pcw &= GENMASK(pll->pcwbits - 1, 0);
  173. return __mtk_pll_recalc_rate(pll, priv->tree->xtal2_rate,
  174. pcw, postdiv);
  175. }
  176. static int mtk_apmixedsys_enable(struct clk *clk)
  177. {
  178. struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  179. const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
  180. u32 r;
  181. r = readl(priv->base + pll->pwr_reg) | CON0_PWR_ON;
  182. writel(r, priv->base + pll->pwr_reg);
  183. udelay(1);
  184. r = readl(priv->base + pll->pwr_reg) & ~CON0_ISO_EN;
  185. writel(r, priv->base + pll->pwr_reg);
  186. udelay(1);
  187. r = readl(priv->base + pll->reg + REG_CON0);
  188. r |= pll->en_mask;
  189. writel(r, priv->base + pll->reg + REG_CON0);
  190. udelay(20);
  191. if (pll->flags & HAVE_RST_BAR) {
  192. r = readl(priv->base + pll->reg + REG_CON0);
  193. r |= pll->rst_bar_mask;
  194. writel(r, priv->base + pll->reg + REG_CON0);
  195. }
  196. return 0;
  197. }
  198. static int mtk_apmixedsys_disable(struct clk *clk)
  199. {
  200. struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  201. const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
  202. u32 r;
  203. if (pll->flags & HAVE_RST_BAR) {
  204. r = readl(priv->base + pll->reg + REG_CON0);
  205. r &= ~pll->rst_bar_mask;
  206. writel(r, priv->base + pll->reg + REG_CON0);
  207. }
  208. r = readl(priv->base + pll->reg + REG_CON0);
  209. r &= ~CON0_BASE_EN;
  210. writel(r, priv->base + pll->reg + REG_CON0);
  211. r = readl(priv->base + pll->pwr_reg) | CON0_ISO_EN;
  212. writel(r, priv->base + pll->pwr_reg);
  213. r = readl(priv->base + pll->pwr_reg) & ~CON0_PWR_ON;
  214. writel(r, priv->base + pll->pwr_reg);
  215. return 0;
  216. }
  217. /* topckgen functions */
  218. static ulong mtk_factor_recalc_rate(const struct mtk_fixed_factor *fdiv,
  219. ulong parent_rate)
  220. {
  221. u64 rate = parent_rate * fdiv->mult;
  222. do_div(rate, fdiv->div);
  223. return rate;
  224. }
  225. static ulong mtk_topckgen_get_factor_rate(struct clk *clk, u32 off)
  226. {
  227. struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  228. const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off];
  229. ulong rate;
  230. switch (fdiv->flags & CLK_PARENT_MASK) {
  231. case CLK_PARENT_APMIXED:
  232. rate = mtk_clk_find_parent_rate(clk, fdiv->parent,
  233. DM_GET_DRIVER(mtk_clk_apmixedsys));
  234. break;
  235. case CLK_PARENT_TOPCKGEN:
  236. rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
  237. break;
  238. default:
  239. rate = priv->tree->xtal_rate;
  240. }
  241. return mtk_factor_recalc_rate(fdiv, rate);
  242. }
  243. static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off)
  244. {
  245. struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  246. const struct mtk_composite *mux = &priv->tree->muxes[off];
  247. u32 index;
  248. index = readl(priv->base + mux->mux_reg);
  249. index &= mux->mux_mask << mux->mux_shift;
  250. index = index >> mux->mux_shift;
  251. if (mux->parent[index])
  252. return mtk_clk_find_parent_rate(clk, mux->parent[index],
  253. NULL);
  254. return priv->tree->xtal_rate;
  255. }
  256. static ulong mtk_topckgen_get_rate(struct clk *clk)
  257. {
  258. struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  259. if (clk->id < priv->tree->fdivs_offs)
  260. return priv->tree->fclks[clk->id].rate;
  261. else if (clk->id < priv->tree->muxes_offs)
  262. return mtk_topckgen_get_factor_rate(clk, clk->id -
  263. priv->tree->fdivs_offs);
  264. else
  265. return mtk_topckgen_get_mux_rate(clk, clk->id -
  266. priv->tree->muxes_offs);
  267. }
  268. static int mtk_topckgen_enable(struct clk *clk)
  269. {
  270. struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  271. const struct mtk_composite *mux;
  272. u32 val;
  273. if (clk->id < priv->tree->muxes_offs)
  274. return 0;
  275. mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs];
  276. if (mux->gate_shift < 0)
  277. return 0;
  278. /* enable clock gate */
  279. if (mux->flags & CLK_MUX_SETCLR_UPD) {
  280. val = BIT(mux->gate_shift);
  281. writel(val, priv->base + mux->mux_clr_reg);
  282. } else {
  283. val = readl(priv->base + mux->gate_reg);
  284. val &= ~BIT(mux->gate_shift);
  285. writel(val, priv->base + mux->gate_reg);
  286. }
  287. if (mux->flags & CLK_DOMAIN_SCPSYS) {
  288. /* enable scpsys clock off control */
  289. writel(SCP_ARMCK_OFF_EN, priv->base + CLK_SCP_CFG0);
  290. writel(SCP_AXICK_DCM_DIS_EN | SCP_AXICK_26M_SEL_EN,
  291. priv->base + CLK_SCP_CFG1);
  292. }
  293. return 0;
  294. }
  295. static int mtk_topckgen_disable(struct clk *clk)
  296. {
  297. struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  298. const struct mtk_composite *mux;
  299. u32 val;
  300. if (clk->id < priv->tree->muxes_offs)
  301. return 0;
  302. mux = &priv->tree->muxes[clk->id - priv->tree->muxes_offs];
  303. if (mux->gate_shift < 0)
  304. return 0;
  305. /* disable clock gate */
  306. if (mux->flags & CLK_MUX_SETCLR_UPD) {
  307. val = BIT(mux->gate_shift);
  308. writel(val, priv->base + mux->mux_set_reg);
  309. } else {
  310. val = readl(priv->base + mux->gate_reg);
  311. val |= BIT(mux->gate_shift);
  312. writel(val, priv->base + mux->gate_reg);
  313. }
  314. return 0;
  315. }
  316. static int mtk_topckgen_set_parent(struct clk *clk, struct clk *parent)
  317. {
  318. struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  319. if (clk->id < priv->tree->muxes_offs)
  320. return 0;
  321. return mtk_clk_mux_set_parent(priv->base, parent->id,
  322. &priv->tree->muxes[clk->id - priv->tree->muxes_offs]);
  323. }
  324. /* CG functions */
  325. static int mtk_clk_gate_enable(struct clk *clk)
  326. {
  327. struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
  328. const struct mtk_gate *gate = &priv->gates[clk->id];
  329. u32 bit = BIT(gate->shift);
  330. switch (gate->flags & CLK_GATE_MASK) {
  331. case CLK_GATE_SETCLR:
  332. writel(bit, priv->base + gate->regs->clr_ofs);
  333. break;
  334. case CLK_GATE_SETCLR_INV:
  335. writel(bit, priv->base + gate->regs->set_ofs);
  336. break;
  337. case CLK_GATE_NO_SETCLR:
  338. clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, 0);
  339. break;
  340. case CLK_GATE_NO_SETCLR_INV:
  341. clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit);
  342. break;
  343. default:
  344. return -EINVAL;
  345. }
  346. return 0;
  347. }
  348. static int mtk_clk_gate_disable(struct clk *clk)
  349. {
  350. struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
  351. const struct mtk_gate *gate = &priv->gates[clk->id];
  352. u32 bit = BIT(gate->shift);
  353. switch (gate->flags & CLK_GATE_MASK) {
  354. case CLK_GATE_SETCLR:
  355. writel(bit, priv->base + gate->regs->set_ofs);
  356. break;
  357. case CLK_GATE_SETCLR_INV:
  358. writel(bit, priv->base + gate->regs->clr_ofs);
  359. break;
  360. case CLK_GATE_NO_SETCLR:
  361. clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit);
  362. break;
  363. case CLK_GATE_NO_SETCLR_INV:
  364. clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, 0);
  365. break;
  366. default:
  367. return -EINVAL;
  368. }
  369. return 0;
  370. }
  371. static ulong mtk_clk_gate_get_rate(struct clk *clk)
  372. {
  373. struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
  374. const struct mtk_gate *gate = &priv->gates[clk->id];
  375. switch (gate->flags & CLK_PARENT_MASK) {
  376. case CLK_PARENT_APMIXED:
  377. return mtk_clk_find_parent_rate(clk, gate->parent,
  378. DM_GET_DRIVER(mtk_clk_apmixedsys));
  379. break;
  380. case CLK_PARENT_TOPCKGEN:
  381. return mtk_clk_find_parent_rate(clk, gate->parent,
  382. DM_GET_DRIVER(mtk_clk_topckgen));
  383. break;
  384. default:
  385. return priv->tree->xtal_rate;
  386. }
  387. }
  388. const struct clk_ops mtk_clk_apmixedsys_ops = {
  389. .enable = mtk_apmixedsys_enable,
  390. .disable = mtk_apmixedsys_disable,
  391. .set_rate = mtk_apmixedsys_set_rate,
  392. .get_rate = mtk_apmixedsys_get_rate,
  393. };
  394. const struct clk_ops mtk_clk_topckgen_ops = {
  395. .enable = mtk_topckgen_enable,
  396. .disable = mtk_topckgen_disable,
  397. .get_rate = mtk_topckgen_get_rate,
  398. .set_parent = mtk_topckgen_set_parent,
  399. };
  400. const struct clk_ops mtk_clk_gate_ops = {
  401. .enable = mtk_clk_gate_enable,
  402. .disable = mtk_clk_gate_disable,
  403. .get_rate = mtk_clk_gate_get_rate,
  404. };
  405. int mtk_common_clk_init(struct udevice *dev,
  406. const struct mtk_clk_tree *tree)
  407. {
  408. struct mtk_clk_priv *priv = dev_get_priv(dev);
  409. priv->base = dev_read_addr_ptr(dev);
  410. if (!priv->base)
  411. return -ENOENT;
  412. priv->tree = tree;
  413. return 0;
  414. }
  415. int mtk_common_clk_gate_init(struct udevice *dev,
  416. const struct mtk_clk_tree *tree,
  417. const struct mtk_gate *gates)
  418. {
  419. struct mtk_cg_priv *priv = dev_get_priv(dev);
  420. priv->base = dev_read_addr_ptr(dev);
  421. if (!priv->base)
  422. return -ENOENT;
  423. priv->tree = tree;
  424. priv->gates = gates;
  425. return 0;
  426. }