clk-imx8mn.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2019 NXP
  4. * Peng Fan <peng.fan@nxp.com>
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <clk-uclass.h>
  9. #include <dm.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <dt-bindings/clock/imx8mn-clock.h>
  13. #include "clk.h"
  14. #define PLL_1416X_RATE(_rate, _m, _p, _s) \
  15. { \
  16. .rate = (_rate), \
  17. .mdiv = (_m), \
  18. .pdiv = (_p), \
  19. .sdiv = (_s), \
  20. }
  21. #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
  22. { \
  23. .rate = (_rate), \
  24. .mdiv = (_m), \
  25. .pdiv = (_p), \
  26. .sdiv = (_s), \
  27. .kdiv = (_k), \
  28. }
  29. static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
  30. PLL_1416X_RATE(1800000000U, 225, 3, 0),
  31. PLL_1416X_RATE(1600000000U, 200, 3, 0),
  32. PLL_1416X_RATE(1200000000U, 300, 3, 1),
  33. PLL_1416X_RATE(1000000000U, 250, 3, 1),
  34. PLL_1416X_RATE(800000000U, 200, 3, 1),
  35. PLL_1416X_RATE(750000000U, 250, 2, 2),
  36. PLL_1416X_RATE(700000000U, 350, 3, 2),
  37. PLL_1416X_RATE(600000000U, 300, 3, 2),
  38. };
  39. static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
  40. PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
  41. };
  42. static struct imx_pll14xx_clk imx8mn_dram_pll __initdata = {
  43. .type = PLL_1443X,
  44. .rate_table = imx8mn_drampll_tbl,
  45. .rate_count = ARRAY_SIZE(imx8mn_drampll_tbl),
  46. };
  47. static struct imx_pll14xx_clk imx8mn_arm_pll __initdata = {
  48. .type = PLL_1416X,
  49. .rate_table = imx8mn_pll1416x_tbl,
  50. .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
  51. };
  52. static struct imx_pll14xx_clk imx8mn_sys_pll __initdata = {
  53. .type = PLL_1416X,
  54. .rate_table = imx8mn_pll1416x_tbl,
  55. .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
  56. };
  57. static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
  58. static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
  59. static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
  60. static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
  61. static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
  62. static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
  63. static const char *imx8mn_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
  64. "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
  65. static const char *imx8mn_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
  66. "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
  67. static const char *imx8mn_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
  68. "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
  69. static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
  70. "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
  71. static const char *imx8mn_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
  72. "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
  73. static const char *imx8mn_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
  74. "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
  75. static const char *imx8mn_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
  76. "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
  77. static const char *imx8mn_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
  78. "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
  79. static const char *imx8mn_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
  80. "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
  81. static const char *imx8mn_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
  82. "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
  83. static const char *imx8mn_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
  84. "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
  85. static const char *imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
  86. "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };
  87. static ulong imx8mn_clk_get_rate(struct clk *clk)
  88. {
  89. struct clk *c;
  90. int ret;
  91. debug("%s(#%lu)\n", __func__, clk->id);
  92. ret = clk_get_by_id(clk->id, &c);
  93. if (ret)
  94. return ret;
  95. return clk_get_rate(c);
  96. }
  97. static ulong imx8mn_clk_set_rate(struct clk *clk, unsigned long rate)
  98. {
  99. struct clk *c;
  100. int ret;
  101. debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
  102. ret = clk_get_by_id(clk->id, &c);
  103. if (ret)
  104. return ret;
  105. return clk_set_rate(c, rate);
  106. }
  107. static int __imx8mn_clk_enable(struct clk *clk, bool enable)
  108. {
  109. struct clk *c;
  110. int ret;
  111. debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
  112. ret = clk_get_by_id(clk->id, &c);
  113. if (ret)
  114. return ret;
  115. if (enable)
  116. ret = clk_enable(c);
  117. else
  118. ret = clk_disable(c);
  119. return ret;
  120. }
  121. static int imx8mn_clk_disable(struct clk *clk)
  122. {
  123. return __imx8mn_clk_enable(clk, 0);
  124. }
  125. static int imx8mn_clk_enable(struct clk *clk)
  126. {
  127. return __imx8mn_clk_enable(clk, 1);
  128. }
  129. static struct clk_ops imx8mn_clk_ops = {
  130. .set_rate = imx8mn_clk_set_rate,
  131. .get_rate = imx8mn_clk_get_rate,
  132. .enable = imx8mn_clk_enable,
  133. .disable = imx8mn_clk_disable,
  134. };
  135. static int imx8mn_clk_probe(struct udevice *dev)
  136. {
  137. void __iomem *base;
  138. base = (void *)ANATOP_BASE_ADDR;
  139. clk_dm(IMX8MN_DRAM_PLL_REF_SEL,
  140. imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
  141. pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  142. clk_dm(IMX8MN_ARM_PLL_REF_SEL,
  143. imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
  144. pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  145. clk_dm(IMX8MN_SYS_PLL1_REF_SEL,
  146. imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
  147. pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  148. clk_dm(IMX8MN_SYS_PLL2_REF_SEL,
  149. imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
  150. pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  151. clk_dm(IMX8MN_SYS_PLL3_REF_SEL,
  152. imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
  153. pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  154. clk_dm(IMX8MN_DRAM_PLL,
  155. imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
  156. base + 0x50, &imx8mn_dram_pll));
  157. clk_dm(IMX8MN_ARM_PLL,
  158. imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
  159. base + 0x84, &imx8mn_arm_pll));
  160. clk_dm(IMX8MN_SYS_PLL1,
  161. imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
  162. base + 0x94, &imx8mn_sys_pll));
  163. clk_dm(IMX8MN_SYS_PLL2,
  164. imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
  165. base + 0x104, &imx8mn_sys_pll));
  166. clk_dm(IMX8MN_SYS_PLL3,
  167. imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
  168. base + 0x114, &imx8mn_sys_pll));
  169. /* PLL bypass out */
  170. clk_dm(IMX8MN_DRAM_PLL_BYPASS,
  171. imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
  172. dram_pll_bypass_sels,
  173. ARRAY_SIZE(dram_pll_bypass_sels),
  174. CLK_SET_RATE_PARENT));
  175. clk_dm(IMX8MN_ARM_PLL_BYPASS,
  176. imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
  177. arm_pll_bypass_sels,
  178. ARRAY_SIZE(arm_pll_bypass_sels),
  179. CLK_SET_RATE_PARENT));
  180. clk_dm(IMX8MN_SYS_PLL1_BYPASS,
  181. imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
  182. sys_pll1_bypass_sels,
  183. ARRAY_SIZE(sys_pll1_bypass_sels),
  184. CLK_SET_RATE_PARENT));
  185. clk_dm(IMX8MN_SYS_PLL2_BYPASS,
  186. imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
  187. sys_pll2_bypass_sels,
  188. ARRAY_SIZE(sys_pll2_bypass_sels),
  189. CLK_SET_RATE_PARENT));
  190. clk_dm(IMX8MN_SYS_PLL3_BYPASS,
  191. imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
  192. sys_pll3_bypass_sels,
  193. ARRAY_SIZE(sys_pll3_bypass_sels),
  194. CLK_SET_RATE_PARENT));
  195. /* PLL out gate */
  196. clk_dm(IMX8MN_DRAM_PLL_OUT,
  197. imx_clk_gate("dram_pll_out", "dram_pll_bypass",
  198. base + 0x50, 13));
  199. clk_dm(IMX8MN_ARM_PLL_OUT,
  200. imx_clk_gate("arm_pll_out", "arm_pll_bypass",
  201. base + 0x84, 11));
  202. clk_dm(IMX8MN_SYS_PLL1_OUT,
  203. imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
  204. base + 0x94, 11));
  205. clk_dm(IMX8MN_SYS_PLL2_OUT,
  206. imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
  207. base + 0x104, 11));
  208. clk_dm(IMX8MN_SYS_PLL3_OUT,
  209. imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
  210. base + 0x114, 11));
  211. /* SYS PLL fixed output */
  212. clk_dm(IMX8MN_SYS_PLL1_40M,
  213. imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
  214. clk_dm(IMX8MN_SYS_PLL1_80M,
  215. imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
  216. clk_dm(IMX8MN_SYS_PLL1_100M,
  217. imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
  218. clk_dm(IMX8MN_SYS_PLL1_133M,
  219. imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
  220. clk_dm(IMX8MN_SYS_PLL1_160M,
  221. imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
  222. clk_dm(IMX8MN_SYS_PLL1_200M,
  223. imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
  224. clk_dm(IMX8MN_SYS_PLL1_266M,
  225. imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
  226. clk_dm(IMX8MN_SYS_PLL1_400M,
  227. imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
  228. clk_dm(IMX8MN_SYS_PLL1_800M,
  229. imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
  230. clk_dm(IMX8MN_SYS_PLL2_50M,
  231. imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
  232. clk_dm(IMX8MN_SYS_PLL2_100M,
  233. imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
  234. clk_dm(IMX8MN_SYS_PLL2_125M,
  235. imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
  236. clk_dm(IMX8MN_SYS_PLL2_166M,
  237. imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
  238. clk_dm(IMX8MN_SYS_PLL2_200M,
  239. imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
  240. clk_dm(IMX8MN_SYS_PLL2_250M,
  241. imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
  242. clk_dm(IMX8MN_SYS_PLL2_333M,
  243. imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
  244. clk_dm(IMX8MN_SYS_PLL2_500M,
  245. imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
  246. clk_dm(IMX8MN_SYS_PLL2_1000M,
  247. imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
  248. base = dev_read_addr_ptr(dev);
  249. if (!base)
  250. return -EINVAL;
  251. clk_dm(IMX8MN_CLK_A53_SRC,
  252. imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
  253. imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels)));
  254. clk_dm(IMX8MN_CLK_A53_CG,
  255. imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
  256. clk_dm(IMX8MN_CLK_A53_DIV,
  257. imx_clk_divider2("arm_a53_div", "arm_a53_cg",
  258. base + 0x8000, 0, 3));
  259. clk_dm(IMX8MN_CLK_AHB,
  260. imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels,
  261. base + 0x9000));
  262. clk_dm(IMX8MN_CLK_IPG_ROOT,
  263. imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
  264. clk_dm(IMX8MN_CLK_ENET_AXI,
  265. imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels,
  266. base + 0x8880));
  267. clk_dm(IMX8MN_CLK_NAND_USDHC_BUS,
  268. imx8m_clk_composite_critical("nand_usdhc_bus",
  269. imx8mn_nand_usdhc_sels,
  270. base + 0x8900));
  271. /* IP */
  272. clk_dm(IMX8MN_CLK_USDHC1,
  273. imx8m_clk_composite("usdhc1", imx8mn_usdhc1_sels,
  274. base + 0xac00));
  275. clk_dm(IMX8MN_CLK_USDHC2,
  276. imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels,
  277. base + 0xac80));
  278. clk_dm(IMX8MN_CLK_I2C1,
  279. imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00));
  280. clk_dm(IMX8MN_CLK_I2C2,
  281. imx8m_clk_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80));
  282. clk_dm(IMX8MN_CLK_I2C3,
  283. imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00));
  284. clk_dm(IMX8MN_CLK_I2C4,
  285. imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80));
  286. clk_dm(IMX8MN_CLK_WDOG,
  287. imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900));
  288. clk_dm(IMX8MN_CLK_USDHC3,
  289. imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels,
  290. base + 0xbc80));
  291. clk_dm(IMX8MN_CLK_I2C1_ROOT,
  292. imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
  293. clk_dm(IMX8MN_CLK_I2C2_ROOT,
  294. imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
  295. clk_dm(IMX8MN_CLK_I2C3_ROOT,
  296. imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
  297. clk_dm(IMX8MN_CLK_I2C4_ROOT,
  298. imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
  299. clk_dm(IMX8MN_CLK_OCOTP_ROOT,
  300. imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
  301. clk_dm(IMX8MN_CLK_USDHC1_ROOT,
  302. imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
  303. clk_dm(IMX8MN_CLK_USDHC2_ROOT,
  304. imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
  305. clk_dm(IMX8MN_CLK_WDOG1_ROOT,
  306. imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
  307. clk_dm(IMX8MN_CLK_WDOG2_ROOT,
  308. imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
  309. clk_dm(IMX8MN_CLK_WDOG3_ROOT,
  310. imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
  311. clk_dm(IMX8MN_CLK_USDHC3_ROOT,
  312. imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
  313. #ifdef CONFIG_SPL_BUILD
  314. struct clk *clkp, *clkp1;
  315. clk_get_by_id(IMX8MN_CLK_WDOG1_ROOT, &clkp);
  316. clk_enable(clkp);
  317. clk_get_by_id(IMX8MN_CLK_WDOG2_ROOT, &clkp);
  318. clk_enable(clkp);
  319. clk_get_by_id(IMX8MN_CLK_WDOG3_ROOT, &clkp);
  320. clk_enable(clkp);
  321. /* Configure SYS_PLL3 to 600MHz */
  322. clk_get_by_id(IMX8MN_SYS_PLL3, &clkp);
  323. clk_set_rate(clkp, 600000000UL);
  324. clk_enable(clkp);
  325. /* Configure ARM to sys_pll2_500m */
  326. clk_get_by_id(IMX8MN_CLK_A53_SRC, &clkp);
  327. clk_get_by_id(IMX8MN_SYS_PLL2_OUT, &clkp1);
  328. clk_enable(clkp1);
  329. clk_get_by_id(IMX8MN_SYS_PLL2_500M, &clkp1);
  330. clk_set_parent(clkp, clkp1);
  331. /* Configure ARM PLL to 1.2GHz */
  332. clk_get_by_id(IMX8MN_ARM_PLL, &clkp1);
  333. clk_set_rate(clkp1, 1200000000UL);
  334. clk_get_by_id(IMX8MN_ARM_PLL_OUT, &clkp1);
  335. clk_enable(clkp1);
  336. clk_set_parent(clkp, clkp1);
  337. /* Configure DIV to 1.2GHz */
  338. clk_get_by_id(IMX8MN_CLK_A53_DIV, &clkp1);
  339. clk_set_rate(clkp1, 1200000000UL);
  340. #endif
  341. return 0;
  342. }
  343. static const struct udevice_id imx8mn_clk_ids[] = {
  344. { .compatible = "fsl,imx8mn-ccm" },
  345. { },
  346. };
  347. U_BOOT_DRIVER(imx8mn_clk) = {
  348. .name = "clk_imx8mn",
  349. .id = UCLASS_CLK,
  350. .of_match = imx8mn_clk_ids,
  351. .ops = &imx8mn_clk_ops,
  352. .probe = imx8mn_clk_probe,
  353. .flags = DM_FLAG_PRE_RELOC,
  354. };