clk-imx8mm.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2019 NXP
  4. * Peng Fan <peng.fan@nxp.com>
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <clk-uclass.h>
  9. #include <dm.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <dt-bindings/clock/imx8mm-clock.h>
  13. #include "clk.h"
  14. #define PLL_1416X_RATE(_rate, _m, _p, _s) \
  15. { \
  16. .rate = (_rate), \
  17. .mdiv = (_m), \
  18. .pdiv = (_p), \
  19. .sdiv = (_s), \
  20. }
  21. #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
  22. { \
  23. .rate = (_rate), \
  24. .mdiv = (_m), \
  25. .pdiv = (_p), \
  26. .sdiv = (_s), \
  27. .kdiv = (_k), \
  28. }
  29. static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
  30. PLL_1416X_RATE(1800000000U, 225, 3, 0),
  31. PLL_1416X_RATE(1600000000U, 200, 3, 0),
  32. PLL_1416X_RATE(1200000000U, 300, 3, 1),
  33. PLL_1416X_RATE(1000000000U, 250, 3, 1),
  34. PLL_1416X_RATE(800000000U, 200, 3, 1),
  35. PLL_1416X_RATE(750000000U, 250, 2, 2),
  36. PLL_1416X_RATE(700000000U, 350, 3, 2),
  37. PLL_1416X_RATE(600000000U, 300, 3, 2),
  38. };
  39. static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
  40. PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
  41. };
  42. static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = {
  43. .type = PLL_1443X,
  44. .rate_table = imx8mm_drampll_tbl,
  45. .rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
  46. };
  47. static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = {
  48. .type = PLL_1416X,
  49. .rate_table = imx8mm_pll1416x_tbl,
  50. .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
  51. };
  52. static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = {
  53. .type = PLL_1416X,
  54. .rate_table = imx8mm_pll1416x_tbl,
  55. .rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
  56. };
  57. static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
  58. static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
  59. static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
  60. static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
  61. static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
  62. static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
  63. static const char *imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
  64. "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
  65. static const char *imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
  66. "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
  67. static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
  68. "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
  69. #ifndef CONFIG_SPL_BUILD
  70. static const char *imx8mm_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m", "sys_pll2_100m",
  71. "sys_pll1_160m", "audio_pll1_out", "video_pll1_out", "clk_ext4", };
  72. static const char *imx8mm_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out", "clk_ext1", "clk_ext2",
  73. "clk_ext3", "clk_ext4", "video_pll1_out", };
  74. static const char *imx8mm_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
  75. "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", };
  76. #endif
  77. static const char *imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
  78. "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
  79. static const char *imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
  80. "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
  81. static const char *imx8mm_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
  82. "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
  83. static const char *imx8mm_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
  84. "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
  85. static const char *imx8mm_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
  86. "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
  87. static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
  88. "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
  89. static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
  90. "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
  91. static const char *imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
  92. "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
  93. static const char *imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
  94. "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };
  95. static ulong imx8mm_clk_get_rate(struct clk *clk)
  96. {
  97. struct clk *c;
  98. int ret;
  99. debug("%s(#%lu)\n", __func__, clk->id);
  100. ret = clk_get_by_id(clk->id, &c);
  101. if (ret)
  102. return ret;
  103. return clk_get_rate(c);
  104. }
  105. static ulong imx8mm_clk_set_rate(struct clk *clk, unsigned long rate)
  106. {
  107. struct clk *c;
  108. int ret;
  109. debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
  110. ret = clk_get_by_id(clk->id, &c);
  111. if (ret)
  112. return ret;
  113. return clk_set_rate(c, rate);
  114. }
  115. static int __imx8mm_clk_enable(struct clk *clk, bool enable)
  116. {
  117. struct clk *c;
  118. int ret;
  119. debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
  120. ret = clk_get_by_id(clk->id, &c);
  121. if (ret)
  122. return ret;
  123. if (enable)
  124. ret = clk_enable(c);
  125. else
  126. ret = clk_disable(c);
  127. return ret;
  128. }
  129. static int imx8mm_clk_disable(struct clk *clk)
  130. {
  131. return __imx8mm_clk_enable(clk, 0);
  132. }
  133. static int imx8mm_clk_enable(struct clk *clk)
  134. {
  135. return __imx8mm_clk_enable(clk, 1);
  136. }
  137. static int imx8mm_clk_set_parent(struct clk *clk, struct clk *parent)
  138. {
  139. struct clk *c, *cp;
  140. int ret;
  141. debug("%s(#%lu), parent: %lu\n", __func__, clk->id, parent->id);
  142. ret = clk_get_by_id(clk->id, &c);
  143. if (ret)
  144. return ret;
  145. ret = clk_get_by_id(parent->id, &cp);
  146. if (ret)
  147. return ret;
  148. return clk_set_parent(c, cp);
  149. }
  150. static struct clk_ops imx8mm_clk_ops = {
  151. .set_rate = imx8mm_clk_set_rate,
  152. .get_rate = imx8mm_clk_get_rate,
  153. .enable = imx8mm_clk_enable,
  154. .disable = imx8mm_clk_disable,
  155. .set_parent = imx8mm_clk_set_parent,
  156. };
  157. static int imx8mm_clk_probe(struct udevice *dev)
  158. {
  159. void __iomem *base;
  160. base = (void *)ANATOP_BASE_ADDR;
  161. clk_dm(IMX8MM_DRAM_PLL_REF_SEL,
  162. imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
  163. pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  164. clk_dm(IMX8MM_ARM_PLL_REF_SEL,
  165. imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
  166. pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  167. clk_dm(IMX8MM_SYS_PLL1_REF_SEL,
  168. imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
  169. pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  170. clk_dm(IMX8MM_SYS_PLL2_REF_SEL,
  171. imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
  172. pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  173. clk_dm(IMX8MM_SYS_PLL3_REF_SEL,
  174. imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
  175. pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
  176. clk_dm(IMX8MM_DRAM_PLL,
  177. imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
  178. base + 0x50, &imx8mm_dram_pll));
  179. clk_dm(IMX8MM_ARM_PLL,
  180. imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
  181. base + 0x84, &imx8mm_arm_pll));
  182. clk_dm(IMX8MM_SYS_PLL1,
  183. imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
  184. base + 0x94, &imx8mm_sys_pll));
  185. clk_dm(IMX8MM_SYS_PLL2,
  186. imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
  187. base + 0x104, &imx8mm_sys_pll));
  188. clk_dm(IMX8MM_SYS_PLL3,
  189. imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
  190. base + 0x114, &imx8mm_sys_pll));
  191. /* PLL bypass out */
  192. clk_dm(IMX8MM_DRAM_PLL_BYPASS,
  193. imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
  194. dram_pll_bypass_sels,
  195. ARRAY_SIZE(dram_pll_bypass_sels),
  196. CLK_SET_RATE_PARENT));
  197. clk_dm(IMX8MM_ARM_PLL_BYPASS,
  198. imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
  199. arm_pll_bypass_sels,
  200. ARRAY_SIZE(arm_pll_bypass_sels),
  201. CLK_SET_RATE_PARENT));
  202. clk_dm(IMX8MM_SYS_PLL1_BYPASS,
  203. imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
  204. sys_pll1_bypass_sels,
  205. ARRAY_SIZE(sys_pll1_bypass_sels),
  206. CLK_SET_RATE_PARENT));
  207. clk_dm(IMX8MM_SYS_PLL2_BYPASS,
  208. imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
  209. sys_pll2_bypass_sels,
  210. ARRAY_SIZE(sys_pll2_bypass_sels),
  211. CLK_SET_RATE_PARENT));
  212. clk_dm(IMX8MM_SYS_PLL3_BYPASS,
  213. imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
  214. sys_pll3_bypass_sels,
  215. ARRAY_SIZE(sys_pll3_bypass_sels),
  216. CLK_SET_RATE_PARENT));
  217. /* PLL out gate */
  218. clk_dm(IMX8MM_DRAM_PLL_OUT,
  219. imx_clk_gate("dram_pll_out", "dram_pll_bypass",
  220. base + 0x50, 13));
  221. clk_dm(IMX8MM_ARM_PLL_OUT,
  222. imx_clk_gate("arm_pll_out", "arm_pll_bypass",
  223. base + 0x84, 11));
  224. clk_dm(IMX8MM_SYS_PLL1_OUT,
  225. imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
  226. base + 0x94, 11));
  227. clk_dm(IMX8MM_SYS_PLL2_OUT,
  228. imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
  229. base + 0x104, 11));
  230. clk_dm(IMX8MM_SYS_PLL3_OUT,
  231. imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
  232. base + 0x114, 11));
  233. /* SYS PLL fixed output */
  234. clk_dm(IMX8MM_SYS_PLL1_40M,
  235. imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
  236. clk_dm(IMX8MM_SYS_PLL1_80M,
  237. imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
  238. clk_dm(IMX8MM_SYS_PLL1_100M,
  239. imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
  240. clk_dm(IMX8MM_SYS_PLL1_133M,
  241. imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
  242. clk_dm(IMX8MM_SYS_PLL1_160M,
  243. imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
  244. clk_dm(IMX8MM_SYS_PLL1_200M,
  245. imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
  246. clk_dm(IMX8MM_SYS_PLL1_266M,
  247. imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
  248. clk_dm(IMX8MM_SYS_PLL1_400M,
  249. imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
  250. clk_dm(IMX8MM_SYS_PLL1_800M,
  251. imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
  252. clk_dm(IMX8MM_SYS_PLL2_50M,
  253. imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
  254. clk_dm(IMX8MM_SYS_PLL2_100M,
  255. imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
  256. clk_dm(IMX8MM_SYS_PLL2_125M,
  257. imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
  258. clk_dm(IMX8MM_SYS_PLL2_166M,
  259. imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
  260. clk_dm(IMX8MM_SYS_PLL2_200M,
  261. imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
  262. clk_dm(IMX8MM_SYS_PLL2_250M,
  263. imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
  264. clk_dm(IMX8MM_SYS_PLL2_333M,
  265. imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
  266. clk_dm(IMX8MM_SYS_PLL2_500M,
  267. imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
  268. clk_dm(IMX8MM_SYS_PLL2_1000M,
  269. imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
  270. base = dev_read_addr_ptr(dev);
  271. if (!base)
  272. return -EINVAL;
  273. clk_dm(IMX8MM_CLK_A53_SRC,
  274. imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
  275. imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels)));
  276. clk_dm(IMX8MM_CLK_A53_CG,
  277. imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
  278. clk_dm(IMX8MM_CLK_A53_DIV,
  279. imx_clk_divider2("arm_a53_div", "arm_a53_cg",
  280. base + 0x8000, 0, 3));
  281. clk_dm(IMX8MM_CLK_AHB,
  282. imx8m_clk_composite_critical("ahb", imx8mm_ahb_sels,
  283. base + 0x9000));
  284. clk_dm(IMX8MM_CLK_IPG_ROOT,
  285. imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
  286. clk_dm(IMX8MM_CLK_ENET_AXI,
  287. imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels,
  288. base + 0x8880));
  289. clk_dm(IMX8MM_CLK_NAND_USDHC_BUS,
  290. imx8m_clk_composite_critical("nand_usdhc_bus",
  291. imx8mm_nand_usdhc_sels,
  292. base + 0x8900));
  293. /* IP */
  294. clk_dm(IMX8MM_CLK_USDHC1,
  295. imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels,
  296. base + 0xac00));
  297. clk_dm(IMX8MM_CLK_USDHC2,
  298. imx8m_clk_composite("usdhc2", imx8mm_usdhc2_sels,
  299. base + 0xac80));
  300. clk_dm(IMX8MM_CLK_I2C1,
  301. imx8m_clk_composite("i2c1", imx8mm_i2c1_sels, base + 0xad00));
  302. clk_dm(IMX8MM_CLK_I2C2,
  303. imx8m_clk_composite("i2c2", imx8mm_i2c2_sels, base + 0xad80));
  304. clk_dm(IMX8MM_CLK_I2C3,
  305. imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00));
  306. clk_dm(IMX8MM_CLK_I2C4,
  307. imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80));
  308. clk_dm(IMX8MM_CLK_WDOG,
  309. imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900));
  310. clk_dm(IMX8MM_CLK_USDHC3,
  311. imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels,
  312. base + 0xbc80));
  313. clk_dm(IMX8MM_CLK_I2C1_ROOT,
  314. imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
  315. clk_dm(IMX8MM_CLK_I2C2_ROOT,
  316. imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
  317. clk_dm(IMX8MM_CLK_I2C3_ROOT,
  318. imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
  319. clk_dm(IMX8MM_CLK_I2C4_ROOT,
  320. imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
  321. clk_dm(IMX8MM_CLK_OCOTP_ROOT,
  322. imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
  323. clk_dm(IMX8MM_CLK_USDHC1_ROOT,
  324. imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
  325. clk_dm(IMX8MM_CLK_USDHC2_ROOT,
  326. imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
  327. clk_dm(IMX8MM_CLK_WDOG1_ROOT,
  328. imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
  329. clk_dm(IMX8MM_CLK_WDOG2_ROOT,
  330. imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
  331. clk_dm(IMX8MM_CLK_WDOG3_ROOT,
  332. imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
  333. clk_dm(IMX8MM_CLK_USDHC3_ROOT,
  334. imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
  335. /* clks not needed in SPL stage */
  336. #ifndef CONFIG_SPL_BUILD
  337. clk_dm(IMX8MM_CLK_ENET_REF,
  338. imx8m_clk_composite("enet_ref", imx8mm_enet_ref_sels,
  339. base + 0xa980));
  340. clk_dm(IMX8MM_CLK_ENET_TIMER,
  341. imx8m_clk_composite("enet_timer", imx8mm_enet_timer_sels,
  342. base + 0xaa00));
  343. clk_dm(IMX8MM_CLK_ENET_PHY_REF,
  344. imx8m_clk_composite("enet_phy", imx8mm_enet_phy_sels,
  345. base + 0xaa80));
  346. clk_dm(IMX8MM_CLK_ENET1_ROOT,
  347. imx_clk_gate4("enet1_root_clk", "enet_axi",
  348. base + 0x40a0, 0));
  349. #endif
  350. #ifdef CONFIG_SPL_BUILD
  351. struct clk *clkp, *clkp1;
  352. clk_get_by_id(IMX8MM_CLK_WDOG1_ROOT, &clkp);
  353. clk_enable(clkp);
  354. clk_get_by_id(IMX8MM_CLK_WDOG2_ROOT, &clkp);
  355. clk_enable(clkp);
  356. clk_get_by_id(IMX8MM_CLK_WDOG3_ROOT, &clkp);
  357. clk_enable(clkp);
  358. /* Configure SYS_PLL3 to 750MHz */
  359. clk_get_by_id(IMX8MM_SYS_PLL3, &clkp);
  360. clk_set_rate(clkp, 750000000UL);
  361. clk_enable(clkp);
  362. /* Configure ARM to sys_pll2_500m */
  363. clk_get_by_id(IMX8MM_CLK_A53_SRC, &clkp);
  364. clk_get_by_id(IMX8MM_SYS_PLL2_OUT, &clkp1);
  365. clk_enable(clkp1);
  366. clk_get_by_id(IMX8MM_SYS_PLL2_500M, &clkp1);
  367. clk_set_parent(clkp, clkp1);
  368. /* Configure ARM PLL to 1.2GHz */
  369. clk_get_by_id(IMX8MM_ARM_PLL, &clkp1);
  370. clk_set_rate(clkp1, 1200000000UL);
  371. clk_get_by_id(IMX8MM_ARM_PLL_OUT, &clkp1);
  372. clk_enable(clkp1);
  373. clk_set_parent(clkp, clkp1);
  374. /* Configure DIV to 1.2GHz */
  375. clk_get_by_id(IMX8MM_CLK_A53_DIV, &clkp1);
  376. clk_set_rate(clkp1, 1200000000UL);
  377. #endif
  378. return 0;
  379. }
  380. static const struct udevice_id imx8mm_clk_ids[] = {
  381. { .compatible = "fsl,imx8mm-ccm" },
  382. { },
  383. };
  384. U_BOOT_DRIVER(imx8mm_clk) = {
  385. .name = "clk_imx8mm",
  386. .id = UCLASS_CLK,
  387. .of_match = imx8mm_clk_ids,
  388. .ops = &imx8mm_clk_ops,
  389. .probe = imx8mm_clk_probe,
  390. .flags = DM_FLAG_PRE_RELOC,
  391. };