clk-imx6q.c 5.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 DENX Software Engineering
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  5. */
  6. #include <common.h>
  7. #include <clk-uclass.h>
  8. #include <dm.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <dt-bindings/clock/imx6qdl-clock.h>
  12. #include "clk.h"
  13. static int imx6q_check_id(ulong id)
  14. {
  15. if (id < IMX6QDL_CLK_DUMMY || id >= IMX6QDL_CLK_END) {
  16. printf("%s: Invalid clk ID #%lu\n", __func__, id);
  17. return -EINVAL;
  18. }
  19. return 0;
  20. }
  21. static ulong imx6q_clk_get_rate(struct clk *clk)
  22. {
  23. struct clk *c;
  24. int ret;
  25. debug("%s(#%lu)\n", __func__, clk->id);
  26. ret = imx6q_check_id(clk->id);
  27. if (ret)
  28. return ret;
  29. ret = clk_get_by_id(clk->id, &c);
  30. if (ret)
  31. return ret;
  32. return clk_get_rate(c);
  33. }
  34. static ulong imx6q_clk_set_rate(struct clk *clk, unsigned long rate)
  35. {
  36. debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
  37. return rate;
  38. }
  39. static int __imx6q_clk_enable(struct clk *clk, bool enable)
  40. {
  41. struct clk *c;
  42. int ret = 0;
  43. debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
  44. ret = imx6q_check_id(clk->id);
  45. if (ret)
  46. return ret;
  47. ret = clk_get_by_id(clk->id, &c);
  48. if (ret)
  49. return ret;
  50. if (enable)
  51. ret = clk_enable(c);
  52. else
  53. ret = clk_disable(c);
  54. return ret;
  55. }
  56. static int imx6q_clk_disable(struct clk *clk)
  57. {
  58. return __imx6q_clk_enable(clk, 0);
  59. }
  60. static int imx6q_clk_enable(struct clk *clk)
  61. {
  62. return __imx6q_clk_enable(clk, 1);
  63. }
  64. static struct clk_ops imx6q_clk_ops = {
  65. .set_rate = imx6q_clk_set_rate,
  66. .get_rate = imx6q_clk_get_rate,
  67. .enable = imx6q_clk_enable,
  68. .disable = imx6q_clk_disable,
  69. };
  70. static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
  71. static const char *const periph_sels[] = { "periph_pre", "periph_clk2", };
  72. static const char *const periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m",
  73. "pll2_pfd0_352m", "pll2_198m", };
  74. static int imx6q_clk_probe(struct udevice *dev)
  75. {
  76. void *base;
  77. /* Anatop clocks */
  78. base = (void *)ANATOP_BASE_ADDR;
  79. clk_dm(IMX6QDL_CLK_PLL2,
  80. imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc",
  81. base + 0x30, 0x1));
  82. clk_dm(IMX6QDL_CLK_PLL3_USB_OTG,
  83. imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
  84. base + 0x10, 0x3));
  85. clk_dm(IMX6QDL_CLK_PLL3_60M,
  86. imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8));
  87. clk_dm(IMX6QDL_CLK_PLL2_PFD0_352M,
  88. imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0));
  89. clk_dm(IMX6QDL_CLK_PLL2_PFD2_396M,
  90. imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2));
  91. /* CCM clocks */
  92. base = dev_read_addr_ptr(dev);
  93. if (!base)
  94. return -EINVAL;
  95. clk_dm(IMX6QDL_CLK_USDHC1_SEL,
  96. imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1,
  97. usdhc_sels, ARRAY_SIZE(usdhc_sels)));
  98. clk_dm(IMX6QDL_CLK_USDHC2_SEL,
  99. imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1,
  100. usdhc_sels, ARRAY_SIZE(usdhc_sels)));
  101. clk_dm(IMX6QDL_CLK_USDHC3_SEL,
  102. imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1,
  103. usdhc_sels, ARRAY_SIZE(usdhc_sels)));
  104. clk_dm(IMX6QDL_CLK_USDHC4_SEL,
  105. imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1,
  106. usdhc_sels, ARRAY_SIZE(usdhc_sels)));
  107. clk_dm(IMX6QDL_CLK_USDHC1_PODF,
  108. imx_clk_divider("usdhc1_podf", "usdhc1_sel",
  109. base + 0x24, 11, 3));
  110. clk_dm(IMX6QDL_CLK_USDHC2_PODF,
  111. imx_clk_divider("usdhc2_podf", "usdhc2_sel",
  112. base + 0x24, 16, 3));
  113. clk_dm(IMX6QDL_CLK_USDHC3_PODF,
  114. imx_clk_divider("usdhc3_podf", "usdhc3_sel",
  115. base + 0x24, 19, 3));
  116. clk_dm(IMX6QDL_CLK_USDHC4_PODF,
  117. imx_clk_divider("usdhc4_podf", "usdhc4_sel",
  118. base + 0x24, 22, 3));
  119. clk_dm(IMX6QDL_CLK_ECSPI_ROOT,
  120. imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6));
  121. clk_dm(IMX6QDL_CLK_ECSPI1,
  122. imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
  123. clk_dm(IMX6QDL_CLK_ECSPI2,
  124. imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2));
  125. clk_dm(IMX6QDL_CLK_ECSPI3,
  126. imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4));
  127. clk_dm(IMX6QDL_CLK_ECSPI4,
  128. imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6));
  129. clk_dm(IMX6QDL_CLK_USDHC1,
  130. imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2));
  131. clk_dm(IMX6QDL_CLK_USDHC2,
  132. imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4));
  133. clk_dm(IMX6QDL_CLK_USDHC3,
  134. imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6));
  135. clk_dm(IMX6QDL_CLK_USDHC4,
  136. imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8));
  137. clk_dm(IMX6QDL_CLK_PERIPH_PRE,
  138. imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels,
  139. ARRAY_SIZE(periph_pre_sels)));
  140. clk_dm(IMX6QDL_CLK_PERIPH,
  141. imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48,
  142. 5, periph_sels, ARRAY_SIZE(periph_sels)));
  143. clk_dm(IMX6QDL_CLK_AHB,
  144. imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3,
  145. base + 0x48, 1));
  146. clk_dm(IMX6QDL_CLK_IPG,
  147. imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2));
  148. clk_dm(IMX6QDL_CLK_IPG_PER,
  149. imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6));
  150. clk_dm(IMX6QDL_CLK_I2C1,
  151. imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6));
  152. clk_dm(IMX6QDL_CLK_I2C2,
  153. imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8));
  154. return 0;
  155. }
  156. static const struct udevice_id imx6q_clk_ids[] = {
  157. { .compatible = "fsl,imx6q-ccm" },
  158. { },
  159. };
  160. U_BOOT_DRIVER(imx6q_clk) = {
  161. .name = "clk_imx6q",
  162. .id = UCLASS_CLK,
  163. .of_match = imx6q_clk_ids,
  164. .ops = &imx6q_clk_ops,
  165. .probe = imx6q_clk_probe,
  166. .flags = DM_FLAG_PRE_RELOC,
  167. };