clk-uclass.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Google, Inc
  4. * Written by Simon Glass <sjg@chromium.org>
  5. * Copyright (c) 2016, NVIDIA CORPORATION.
  6. * Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
  7. */
  8. #include <common.h>
  9. #include <clk.h>
  10. #include <clk-uclass.h>
  11. #include <dm.h>
  12. #include <dm/read.h>
  13. #include <dt-structs.h>
  14. #include <errno.h>
  15. #include <linux/clk-provider.h>
  16. static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
  17. {
  18. return (const struct clk_ops *)dev->driver->ops;
  19. }
  20. #if CONFIG_IS_ENABLED(OF_CONTROL)
  21. # if CONFIG_IS_ENABLED(OF_PLATDATA)
  22. int clk_get_by_index_platdata(struct udevice *dev, int index,
  23. struct phandle_1_arg *cells, struct clk *clk)
  24. {
  25. int ret;
  26. if (index != 0)
  27. return -ENOSYS;
  28. ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
  29. if (ret)
  30. return ret;
  31. clk->id = cells[0].arg[0];
  32. return 0;
  33. }
  34. # else
  35. static int clk_of_xlate_default(struct clk *clk,
  36. struct ofnode_phandle_args *args)
  37. {
  38. debug("%s(clk=%p)\n", __func__, clk);
  39. if (args->args_count > 1) {
  40. debug("Invaild args_count: %d\n", args->args_count);
  41. return -EINVAL;
  42. }
  43. if (args->args_count)
  44. clk->id = args->args[0];
  45. else
  46. clk->id = 0;
  47. clk->data = 0;
  48. return 0;
  49. }
  50. static int clk_get_by_index_tail(int ret, ofnode node,
  51. struct ofnode_phandle_args *args,
  52. const char *list_name, int index,
  53. struct clk *clk)
  54. {
  55. struct udevice *dev_clk;
  56. const struct clk_ops *ops;
  57. assert(clk);
  58. clk->dev = NULL;
  59. if (ret)
  60. goto err;
  61. ret = uclass_get_device_by_ofnode(UCLASS_CLK, args->node, &dev_clk);
  62. if (ret) {
  63. debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
  64. __func__, ret);
  65. return ret;
  66. }
  67. clk->dev = dev_clk;
  68. ops = clk_dev_ops(dev_clk);
  69. if (ops->of_xlate)
  70. ret = ops->of_xlate(clk, args);
  71. else
  72. ret = clk_of_xlate_default(clk, args);
  73. if (ret) {
  74. debug("of_xlate() failed: %d\n", ret);
  75. return ret;
  76. }
  77. return clk_request(dev_clk, clk);
  78. err:
  79. debug("%s: Node '%s', property '%s', failed to request CLK index %d: %d\n",
  80. __func__, ofnode_get_name(node), list_name, index, ret);
  81. return ret;
  82. }
  83. static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
  84. int index, struct clk *clk)
  85. {
  86. int ret;
  87. struct ofnode_phandle_args args;
  88. debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
  89. assert(clk);
  90. clk->dev = NULL;
  91. ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
  92. index, &args);
  93. if (ret) {
  94. debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
  95. __func__, ret);
  96. return ret;
  97. }
  98. return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
  99. index > 0, clk);
  100. }
  101. int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
  102. {
  103. struct ofnode_phandle_args args;
  104. int ret;
  105. ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
  106. index, &args);
  107. return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
  108. index > 0, clk);
  109. }
  110. int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk)
  111. {
  112. struct ofnode_phandle_args args;
  113. int ret;
  114. ret = ofnode_parse_phandle_with_args(node, "clocks", "#clock-cells", 0,
  115. index > 0, &args);
  116. return clk_get_by_index_tail(ret, node, &args, "clocks",
  117. index > 0, clk);
  118. }
  119. int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
  120. {
  121. int i, ret, err, count;
  122. bulk->count = 0;
  123. count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
  124. if (count < 1)
  125. return count;
  126. bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL);
  127. if (!bulk->clks)
  128. return -ENOMEM;
  129. for (i = 0; i < count; i++) {
  130. ret = clk_get_by_index(dev, i, &bulk->clks[i]);
  131. if (ret < 0)
  132. goto bulk_get_err;
  133. ++bulk->count;
  134. }
  135. return 0;
  136. bulk_get_err:
  137. err = clk_release_all(bulk->clks, bulk->count);
  138. if (err)
  139. debug("%s: could release all clocks for %p\n",
  140. __func__, dev);
  141. return ret;
  142. }
  143. static int clk_set_default_parents(struct udevice *dev, int stage)
  144. {
  145. struct clk clk, parent_clk;
  146. int index;
  147. int num_parents;
  148. int ret;
  149. num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
  150. "#clock-cells");
  151. if (num_parents < 0) {
  152. debug("%s: could not read assigned-clock-parents for %p\n",
  153. __func__, dev);
  154. return 0;
  155. }
  156. for (index = 0; index < num_parents; index++) {
  157. ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
  158. index, &parent_clk);
  159. /* If -ENOENT, this is a no-op entry */
  160. if (ret == -ENOENT)
  161. continue;
  162. if (ret) {
  163. debug("%s: could not get parent clock %d for %s\n",
  164. __func__, index, dev_read_name(dev));
  165. return ret;
  166. }
  167. ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
  168. index, &clk);
  169. if (ret) {
  170. debug("%s: could not get assigned clock %d for %s\n",
  171. __func__, index, dev_read_name(dev));
  172. return ret;
  173. }
  174. /* This is clk provider device trying to reparent itself
  175. * It cannot be done right now but need to wait after the
  176. * device is probed
  177. */
  178. if (stage == 0 && clk.dev == dev)
  179. continue;
  180. if (stage > 0 && clk.dev != dev)
  181. /* do not setup twice the parent clocks */
  182. continue;
  183. ret = clk_set_parent(&clk, &parent_clk);
  184. /*
  185. * Not all drivers may support clock-reparenting (as of now).
  186. * Ignore errors due to this.
  187. */
  188. if (ret == -ENOSYS)
  189. continue;
  190. if (ret < 0) {
  191. debug("%s: failed to reparent clock %d for %s\n",
  192. __func__, index, dev_read_name(dev));
  193. return ret;
  194. }
  195. }
  196. return 0;
  197. }
  198. static int clk_set_default_rates(struct udevice *dev, int stage)
  199. {
  200. struct clk clk;
  201. int index;
  202. int num_rates;
  203. int size;
  204. int ret = 0;
  205. u32 *rates = NULL;
  206. size = dev_read_size(dev, "assigned-clock-rates");
  207. if (size < 0)
  208. return 0;
  209. num_rates = size / sizeof(u32);
  210. rates = calloc(num_rates, sizeof(u32));
  211. if (!rates)
  212. return -ENOMEM;
  213. ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates);
  214. if (ret)
  215. goto fail;
  216. for (index = 0; index < num_rates; index++) {
  217. /* If 0 is passed, this is a no-op */
  218. if (!rates[index])
  219. continue;
  220. ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
  221. index, &clk);
  222. if (ret) {
  223. debug("%s: could not get assigned clock %d for %s\n",
  224. __func__, index, dev_read_name(dev));
  225. continue;
  226. }
  227. /* This is clk provider device trying to program itself
  228. * It cannot be done right now but need to wait after the
  229. * device is probed
  230. */
  231. if (stage == 0 && clk.dev == dev)
  232. continue;
  233. if (stage > 0 && clk.dev != dev)
  234. /* do not setup twice the parent clocks */
  235. continue;
  236. ret = clk_set_rate(&clk, rates[index]);
  237. if (ret < 0) {
  238. debug("%s: failed to set rate on clock index %d (%ld) for %s\n",
  239. __func__, index, clk.id, dev_read_name(dev));
  240. break;
  241. }
  242. }
  243. fail:
  244. free(rates);
  245. return ret;
  246. }
  247. int clk_set_defaults(struct udevice *dev, int stage)
  248. {
  249. int ret;
  250. if (!dev_of_valid(dev))
  251. return 0;
  252. /* If this not in SPL and pre-reloc state, don't take any action. */
  253. if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
  254. return 0;
  255. debug("%s(%s)\n", __func__, dev_read_name(dev));
  256. ret = clk_set_default_parents(dev, stage);
  257. if (ret)
  258. return ret;
  259. ret = clk_set_default_rates(dev, stage);
  260. if (ret < 0)
  261. return ret;
  262. return 0;
  263. }
  264. int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
  265. {
  266. int index;
  267. debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
  268. clk->dev = NULL;
  269. index = dev_read_stringlist_search(dev, "clock-names", name);
  270. if (index < 0) {
  271. debug("fdt_stringlist_search() failed: %d\n", index);
  272. return index;
  273. }
  274. return clk_get_by_index(dev, index, clk);
  275. }
  276. # endif /* OF_PLATDATA */
  277. int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk)
  278. {
  279. int index;
  280. debug("%s(node=%p, name=%s, clk=%p)\n", __func__,
  281. ofnode_get_name(node), name, clk);
  282. clk->dev = NULL;
  283. index = ofnode_stringlist_search(node, "clock-names", name);
  284. if (index < 0) {
  285. debug("fdt_stringlist_search() failed: %d\n", index);
  286. return index;
  287. }
  288. return clk_get_by_index_nodev(node, index, clk);
  289. }
  290. int clk_get_optional_nodev(ofnode node, const char *name, struct clk *clk)
  291. {
  292. int ret;
  293. ret = clk_get_by_name_nodev(node, name, clk);
  294. if (ret == -ENODATA)
  295. return 0;
  296. return ret;
  297. }
  298. int clk_release_all(struct clk *clk, int count)
  299. {
  300. int i, ret;
  301. for (i = 0; i < count; i++) {
  302. debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
  303. /* check if clock has been previously requested */
  304. if (!clk[i].dev)
  305. continue;
  306. ret = clk_disable(&clk[i]);
  307. if (ret && ret != -ENOSYS)
  308. return ret;
  309. ret = clk_free(&clk[i]);
  310. if (ret && ret != -ENOSYS)
  311. return ret;
  312. }
  313. return 0;
  314. }
  315. #endif /* OF_CONTROL */
  316. int clk_request(struct udevice *dev, struct clk *clk)
  317. {
  318. const struct clk_ops *ops;
  319. debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
  320. if (!clk)
  321. return 0;
  322. ops = clk_dev_ops(dev);
  323. clk->dev = dev;
  324. if (!ops->request)
  325. return 0;
  326. return ops->request(clk);
  327. }
  328. int clk_free(struct clk *clk)
  329. {
  330. const struct clk_ops *ops;
  331. debug("%s(clk=%p)\n", __func__, clk);
  332. if (!clk_valid(clk))
  333. return 0;
  334. ops = clk_dev_ops(clk->dev);
  335. if (!ops->free)
  336. return 0;
  337. return ops->free(clk);
  338. }
  339. ulong clk_get_rate(struct clk *clk)
  340. {
  341. const struct clk_ops *ops;
  342. debug("%s(clk=%p)\n", __func__, clk);
  343. if (!clk_valid(clk))
  344. return 0;
  345. ops = clk_dev_ops(clk->dev);
  346. if (!ops->get_rate)
  347. return -ENOSYS;
  348. return ops->get_rate(clk);
  349. }
  350. struct clk *clk_get_parent(struct clk *clk)
  351. {
  352. struct udevice *pdev;
  353. struct clk *pclk;
  354. debug("%s(clk=%p)\n", __func__, clk);
  355. if (!clk_valid(clk))
  356. return NULL;
  357. pdev = dev_get_parent(clk->dev);
  358. pclk = dev_get_clk_ptr(pdev);
  359. if (!pclk)
  360. return ERR_PTR(-ENODEV);
  361. return pclk;
  362. }
  363. long long clk_get_parent_rate(struct clk *clk)
  364. {
  365. const struct clk_ops *ops;
  366. struct clk *pclk;
  367. debug("%s(clk=%p)\n", __func__, clk);
  368. if (!clk_valid(clk))
  369. return 0;
  370. pclk = clk_get_parent(clk);
  371. if (IS_ERR(pclk))
  372. return -ENODEV;
  373. ops = clk_dev_ops(pclk->dev);
  374. if (!ops->get_rate)
  375. return -ENOSYS;
  376. /* Read the 'rate' if not already set or if proper flag set*/
  377. if (!pclk->rate || pclk->flags & CLK_GET_RATE_NOCACHE)
  378. pclk->rate = clk_get_rate(pclk);
  379. return pclk->rate;
  380. }
  381. ulong clk_set_rate(struct clk *clk, ulong rate)
  382. {
  383. const struct clk_ops *ops;
  384. debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
  385. if (!clk_valid(clk))
  386. return 0;
  387. ops = clk_dev_ops(clk->dev);
  388. if (!ops->set_rate)
  389. return -ENOSYS;
  390. return ops->set_rate(clk, rate);
  391. }
  392. int clk_set_parent(struct clk *clk, struct clk *parent)
  393. {
  394. const struct clk_ops *ops;
  395. debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);
  396. if (!clk_valid(clk))
  397. return 0;
  398. ops = clk_dev_ops(clk->dev);
  399. if (!ops->set_parent)
  400. return -ENOSYS;
  401. return ops->set_parent(clk, parent);
  402. }
  403. int clk_enable(struct clk *clk)
  404. {
  405. const struct clk_ops *ops;
  406. struct clk *clkp = NULL;
  407. int ret;
  408. debug("%s(clk=%p)\n", __func__, clk);
  409. if (!clk_valid(clk))
  410. return 0;
  411. ops = clk_dev_ops(clk->dev);
  412. if (CONFIG_IS_ENABLED(CLK_CCF)) {
  413. /* Take id 0 as a non-valid clk, such as dummy */
  414. if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
  415. if (clkp->enable_count) {
  416. clkp->enable_count++;
  417. return 0;
  418. }
  419. if (clkp->dev->parent &&
  420. device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
  421. ret = clk_enable(dev_get_clk_ptr(clkp->dev->parent));
  422. if (ret) {
  423. printf("Enable %s failed\n",
  424. clkp->dev->parent->name);
  425. return ret;
  426. }
  427. }
  428. }
  429. if (ops->enable) {
  430. ret = ops->enable(clk);
  431. if (ret) {
  432. printf("Enable %s failed\n", clk->dev->name);
  433. return ret;
  434. }
  435. }
  436. if (clkp)
  437. clkp->enable_count++;
  438. } else {
  439. if (!ops->enable)
  440. return -ENOSYS;
  441. return ops->enable(clk);
  442. }
  443. return 0;
  444. }
  445. int clk_enable_bulk(struct clk_bulk *bulk)
  446. {
  447. int i, ret;
  448. for (i = 0; i < bulk->count; i++) {
  449. ret = clk_enable(&bulk->clks[i]);
  450. if (ret < 0 && ret != -ENOSYS)
  451. return ret;
  452. }
  453. return 0;
  454. }
  455. int clk_disable(struct clk *clk)
  456. {
  457. const struct clk_ops *ops;
  458. struct clk *clkp = NULL;
  459. int ret;
  460. debug("%s(clk=%p)\n", __func__, clk);
  461. if (!clk_valid(clk))
  462. return 0;
  463. ops = clk_dev_ops(clk->dev);
  464. if (CONFIG_IS_ENABLED(CLK_CCF)) {
  465. if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
  466. if (clkp->enable_count == 0) {
  467. printf("clk %s already disabled\n",
  468. clkp->dev->name);
  469. return 0;
  470. }
  471. if (--clkp->enable_count > 0)
  472. return 0;
  473. }
  474. if (ops->disable) {
  475. ret = ops->disable(clk);
  476. if (ret)
  477. return ret;
  478. }
  479. if (clkp && clkp->dev->parent &&
  480. device_get_uclass_id(clkp->dev) == UCLASS_CLK) {
  481. ret = clk_disable(dev_get_clk_ptr(clkp->dev->parent));
  482. if (ret) {
  483. printf("Disable %s failed\n",
  484. clkp->dev->parent->name);
  485. return ret;
  486. }
  487. }
  488. } else {
  489. if (!ops->disable)
  490. return -ENOSYS;
  491. return ops->disable(clk);
  492. }
  493. return 0;
  494. }
  495. int clk_disable_bulk(struct clk_bulk *bulk)
  496. {
  497. int i, ret;
  498. for (i = 0; i < bulk->count; i++) {
  499. ret = clk_disable(&bulk->clks[i]);
  500. if (ret < 0 && ret != -ENOSYS)
  501. return ret;
  502. }
  503. return 0;
  504. }
  505. int clk_get_by_id(ulong id, struct clk **clkp)
  506. {
  507. struct udevice *dev;
  508. struct uclass *uc;
  509. int ret;
  510. ret = uclass_get(UCLASS_CLK, &uc);
  511. if (ret)
  512. return ret;
  513. uclass_foreach_dev(dev, uc) {
  514. struct clk *clk = dev_get_clk_ptr(dev);
  515. if (clk && clk->id == id) {
  516. *clkp = clk;
  517. return 0;
  518. }
  519. }
  520. return -ENOENT;
  521. }
  522. bool clk_is_match(const struct clk *p, const struct clk *q)
  523. {
  524. /* trivial case: identical struct clk's or both NULL */
  525. if (p == q)
  526. return true;
  527. /* trivial case #2: on the clk pointer is NULL */
  528. if (!p || !q)
  529. return false;
  530. /* same device, id and data */
  531. if (p->dev == q->dev && p->id == q->id && p->data == q->data)
  532. return true;
  533. return false;
  534. }
  535. static void devm_clk_release(struct udevice *dev, void *res)
  536. {
  537. clk_free(res);
  538. }
  539. static int devm_clk_match(struct udevice *dev, void *res, void *data)
  540. {
  541. return res == data;
  542. }
  543. struct clk *devm_clk_get(struct udevice *dev, const char *id)
  544. {
  545. int rc;
  546. struct clk *clk;
  547. clk = devres_alloc(devm_clk_release, sizeof(struct clk), __GFP_ZERO);
  548. if (unlikely(!clk))
  549. return ERR_PTR(-ENOMEM);
  550. rc = clk_get_by_name(dev, id, clk);
  551. if (rc)
  552. return ERR_PTR(rc);
  553. devres_add(dev, clk);
  554. return clk;
  555. }
  556. struct clk *devm_clk_get_optional(struct udevice *dev, const char *id)
  557. {
  558. struct clk *clk = devm_clk_get(dev, id);
  559. if (PTR_ERR(clk) == -ENODATA)
  560. return NULL;
  561. return clk;
  562. }
  563. void devm_clk_put(struct udevice *dev, struct clk *clk)
  564. {
  565. int rc;
  566. if (!clk)
  567. return;
  568. rc = devres_release(dev, devm_clk_release, devm_clk_match, clk);
  569. WARN_ON(rc);
  570. }
  571. int clk_uclass_post_probe(struct udevice *dev)
  572. {
  573. /*
  574. * when a clock provider is probed. Call clk_set_defaults()
  575. * also after the device is probed. This takes care of cases
  576. * where the DT is used to setup default parents and rates
  577. * using assigned-clocks
  578. */
  579. clk_set_defaults(dev, 1);
  580. return 0;
  581. }
  582. UCLASS_DRIVER(clk) = {
  583. .id = UCLASS_CLK,
  584. .name = "clk",
  585. .post_probe = clk_uclass_post_probe,
  586. };