board.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
  4. * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  5. *
  6. * (C) Copyright 2007-2011
  7. * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  8. * Tom Cubie <tangliang@allwinnertech.com>
  9. *
  10. * Some board init for the Allwinner A10-evb board.
  11. */
  12. #include <common.h>
  13. #include <dm.h>
  14. #include <env.h>
  15. #include <hang.h>
  16. #include <image.h>
  17. #include <init.h>
  18. #include <log.h>
  19. #include <mmc.h>
  20. #include <axp_pmic.h>
  21. #include <generic-phy.h>
  22. #include <phy-sun4i-usb.h>
  23. #include <asm/arch/clock.h>
  24. #include <asm/arch/cpu.h>
  25. #include <asm/arch/display.h>
  26. #include <asm/arch/dram.h>
  27. #include <asm/arch/gpio.h>
  28. #include <asm/arch/mmc.h>
  29. #include <asm/arch/spl.h>
  30. #include <linux/delay.h>
  31. #include <u-boot/crc.h>
  32. #ifndef CONFIG_ARM64
  33. #include <asm/armv7.h>
  34. #endif
  35. #include <asm/gpio.h>
  36. #include <asm/io.h>
  37. #include <u-boot/crc.h>
  38. #include <env_internal.h>
  39. #include <linux/libfdt.h>
  40. #include <nand.h>
  41. #include <net.h>
  42. #include <spl.h>
  43. #include <sy8106a.h>
  44. #include <asm/setup.h>
  45. #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
  46. /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
  47. int soft_i2c_gpio_sda;
  48. int soft_i2c_gpio_scl;
  49. static int soft_i2c_board_init(void)
  50. {
  51. int ret;
  52. soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
  53. if (soft_i2c_gpio_sda < 0) {
  54. printf("Error invalid soft i2c sda pin: '%s', err %d\n",
  55. CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
  56. return soft_i2c_gpio_sda;
  57. }
  58. ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
  59. if (ret) {
  60. printf("Error requesting soft i2c sda pin: '%s', err %d\n",
  61. CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
  62. return ret;
  63. }
  64. soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
  65. if (soft_i2c_gpio_scl < 0) {
  66. printf("Error invalid soft i2c scl pin: '%s', err %d\n",
  67. CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
  68. return soft_i2c_gpio_scl;
  69. }
  70. ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
  71. if (ret) {
  72. printf("Error requesting soft i2c scl pin: '%s', err %d\n",
  73. CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
  74. return ret;
  75. }
  76. return 0;
  77. }
  78. #else
  79. static int soft_i2c_board_init(void) { return 0; }
  80. #endif
  81. DECLARE_GLOBAL_DATA_PTR;
  82. void i2c_init_board(void)
  83. {
  84. #ifdef CONFIG_I2C0_ENABLE
  85. #if defined(CONFIG_MACH_SUN4I) || \
  86. defined(CONFIG_MACH_SUN5I) || \
  87. defined(CONFIG_MACH_SUN7I) || \
  88. defined(CONFIG_MACH_SUN8I_R40)
  89. sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
  90. sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
  91. clock_twi_onoff(0, 1);
  92. #elif defined(CONFIG_MACH_SUN6I)
  93. sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
  94. sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
  95. clock_twi_onoff(0, 1);
  96. #elif defined(CONFIG_MACH_SUN8I)
  97. sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
  98. sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
  99. clock_twi_onoff(0, 1);
  100. #elif defined(CONFIG_MACH_SUN50I)
  101. sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
  102. sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
  103. clock_twi_onoff(0, 1);
  104. #endif
  105. #endif
  106. #ifdef CONFIG_I2C1_ENABLE
  107. #if defined(CONFIG_MACH_SUN4I) || \
  108. defined(CONFIG_MACH_SUN7I) || \
  109. defined(CONFIG_MACH_SUN8I_R40)
  110. sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
  111. sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
  112. clock_twi_onoff(1, 1);
  113. #elif defined(CONFIG_MACH_SUN5I)
  114. sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
  115. sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
  116. clock_twi_onoff(1, 1);
  117. #elif defined(CONFIG_MACH_SUN6I)
  118. sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
  119. sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
  120. clock_twi_onoff(1, 1);
  121. #elif defined(CONFIG_MACH_SUN8I)
  122. sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
  123. sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
  124. clock_twi_onoff(1, 1);
  125. #elif defined(CONFIG_MACH_SUN50I)
  126. sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
  127. sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
  128. clock_twi_onoff(1, 1);
  129. #endif
  130. #endif
  131. #ifdef CONFIG_I2C2_ENABLE
  132. #if defined(CONFIG_MACH_SUN4I) || \
  133. defined(CONFIG_MACH_SUN7I) || \
  134. defined(CONFIG_MACH_SUN8I_R40)
  135. sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
  136. sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
  137. clock_twi_onoff(2, 1);
  138. #elif defined(CONFIG_MACH_SUN5I)
  139. sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
  140. sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
  141. clock_twi_onoff(2, 1);
  142. #elif defined(CONFIG_MACH_SUN6I)
  143. sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
  144. sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
  145. clock_twi_onoff(2, 1);
  146. #elif defined(CONFIG_MACH_SUN8I)
  147. sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
  148. sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
  149. clock_twi_onoff(2, 1);
  150. #elif defined(CONFIG_MACH_SUN50I)
  151. sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
  152. sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
  153. clock_twi_onoff(2, 1);
  154. #endif
  155. #endif
  156. #ifdef CONFIG_I2C3_ENABLE
  157. #if defined(CONFIG_MACH_SUN6I)
  158. sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
  159. sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
  160. clock_twi_onoff(3, 1);
  161. #elif defined(CONFIG_MACH_SUN7I) || \
  162. defined(CONFIG_MACH_SUN8I_R40)
  163. sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
  164. sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
  165. clock_twi_onoff(3, 1);
  166. #endif
  167. #endif
  168. #ifdef CONFIG_I2C4_ENABLE
  169. #if defined(CONFIG_MACH_SUN7I) || \
  170. defined(CONFIG_MACH_SUN8I_R40)
  171. sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
  172. sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
  173. clock_twi_onoff(4, 1);
  174. #endif
  175. #endif
  176. #ifdef CONFIG_R_I2C_ENABLE
  177. #ifdef CONFIG_MACH_SUN50I
  178. clock_twi_onoff(5, 1);
  179. sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
  180. sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
  181. #else
  182. clock_twi_onoff(5, 1);
  183. sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
  184. sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
  185. #endif
  186. #endif
  187. }
  188. #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
  189. enum env_location env_get_location(enum env_operation op, int prio)
  190. {
  191. switch (prio) {
  192. case 0:
  193. return ENVL_FAT;
  194. case 1:
  195. return ENVL_MMC;
  196. default:
  197. return ENVL_UNKNOWN;
  198. }
  199. }
  200. #endif
  201. #ifdef CONFIG_DM_MMC
  202. static void mmc_pinmux_setup(int sdc);
  203. #endif
  204. /* add board specific code here */
  205. int board_init(void)
  206. {
  207. __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
  208. gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
  209. #ifndef CONFIG_ARM64
  210. asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
  211. debug("id_pfr1: 0x%08x\n", id_pfr1);
  212. /* Generic Timer Extension available? */
  213. if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
  214. uint32_t freq;
  215. debug("Setting CNTFRQ\n");
  216. /*
  217. * CNTFRQ is a secure register, so we will crash if we try to
  218. * write this from the non-secure world (read is OK, though).
  219. * In case some bootcode has already set the correct value,
  220. * we avoid the risk of writing to it.
  221. */
  222. asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
  223. if (freq != COUNTER_FREQUENCY) {
  224. debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
  225. freq, COUNTER_FREQUENCY);
  226. #ifdef CONFIG_NON_SECURE
  227. printf("arch timer frequency is wrong, but cannot adjust it\n");
  228. #else
  229. asm volatile("mcr p15, 0, %0, c14, c0, 0"
  230. : : "r"(COUNTER_FREQUENCY));
  231. #endif
  232. }
  233. }
  234. #endif /* !CONFIG_ARM64 */
  235. ret = axp_gpio_init();
  236. if (ret)
  237. return ret;
  238. #ifdef CONFIG_SATAPWR
  239. satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
  240. gpio_request(satapwr_pin, "satapwr");
  241. gpio_direction_output(satapwr_pin, 1);
  242. /* Give attached sata device time to power-up to avoid link timeouts */
  243. mdelay(500);
  244. #endif
  245. #ifdef CONFIG_MACPWR
  246. macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
  247. gpio_request(macpwr_pin, "macpwr");
  248. gpio_direction_output(macpwr_pin, 1);
  249. #endif
  250. #ifdef CONFIG_DM_I2C
  251. /*
  252. * Temporary workaround for enabling I2C clocks until proper sunxi DM
  253. * clk, reset and pinctrl drivers land.
  254. */
  255. i2c_init_board();
  256. #endif
  257. #ifdef CONFIG_DM_MMC
  258. /*
  259. * Temporary workaround for enabling MMC clocks until a sunxi DM
  260. * pinctrl driver lands.
  261. */
  262. mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
  263. #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
  264. mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
  265. #endif
  266. #endif /* CONFIG_DM_MMC */
  267. /* Uses dm gpio code so do this here and not in i2c_init_board() */
  268. return soft_i2c_board_init();
  269. }
  270. /*
  271. * On older SoCs the SPL is actually at address zero, so using NULL as
  272. * an error value does not work.
  273. */
  274. #define INVALID_SPL_HEADER ((void *)~0UL)
  275. static struct boot_file_head * get_spl_header(uint8_t req_version)
  276. {
  277. struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
  278. uint8_t spl_header_version = spl->spl_signature[3];
  279. /* Is there really the SPL header (still) there? */
  280. if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
  281. return INVALID_SPL_HEADER;
  282. if (spl_header_version < req_version) {
  283. printf("sunxi SPL version mismatch: expected %u, got %u\n",
  284. req_version, spl_header_version);
  285. return INVALID_SPL_HEADER;
  286. }
  287. return spl;
  288. }
  289. int dram_init(void)
  290. {
  291. struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
  292. if (spl == INVALID_SPL_HEADER)
  293. gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
  294. PHYS_SDRAM_0_SIZE);
  295. else
  296. gd->ram_size = (phys_addr_t)spl->dram_size << 20;
  297. if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
  298. gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
  299. return 0;
  300. }
  301. #if defined(CONFIG_NAND_SUNXI)
  302. static void nand_pinmux_setup(void)
  303. {
  304. unsigned int pin;
  305. for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
  306. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
  307. #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
  308. for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
  309. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
  310. #endif
  311. /* sun4i / sun7i do have a PC23, but it is not used for nand,
  312. * only sun7i has a PC24 */
  313. #ifdef CONFIG_MACH_SUN7I
  314. sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
  315. #endif
  316. }
  317. static void nand_clock_setup(void)
  318. {
  319. struct sunxi_ccm_reg *const ccm =
  320. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  321. setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
  322. #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
  323. defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
  324. setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
  325. #endif
  326. setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
  327. }
  328. void board_nand_init(void)
  329. {
  330. nand_pinmux_setup();
  331. nand_clock_setup();
  332. #ifndef CONFIG_SPL_BUILD
  333. sunxi_nand_init();
  334. #endif
  335. }
  336. #endif
  337. #ifdef CONFIG_MMC
  338. static void mmc_pinmux_setup(int sdc)
  339. {
  340. unsigned int pin;
  341. __maybe_unused int pins;
  342. switch (sdc) {
  343. case 0:
  344. /* SDC0: PF0-PF5 */
  345. for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
  346. sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
  347. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  348. sunxi_gpio_set_drv(pin, 2);
  349. }
  350. break;
  351. case 1:
  352. pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
  353. #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
  354. defined(CONFIG_MACH_SUN8I_R40)
  355. if (pins == SUNXI_GPIO_H) {
  356. /* SDC1: PH22-PH-27 */
  357. for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
  358. sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
  359. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  360. sunxi_gpio_set_drv(pin, 2);
  361. }
  362. } else {
  363. /* SDC1: PG0-PG5 */
  364. for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
  365. sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
  366. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  367. sunxi_gpio_set_drv(pin, 2);
  368. }
  369. }
  370. #elif defined(CONFIG_MACH_SUN5I)
  371. /* SDC1: PG3-PG8 */
  372. for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
  373. sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
  374. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  375. sunxi_gpio_set_drv(pin, 2);
  376. }
  377. #elif defined(CONFIG_MACH_SUN6I)
  378. /* SDC1: PG0-PG5 */
  379. for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
  380. sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
  381. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  382. sunxi_gpio_set_drv(pin, 2);
  383. }
  384. #elif defined(CONFIG_MACH_SUN8I)
  385. if (pins == SUNXI_GPIO_D) {
  386. /* SDC1: PD2-PD7 */
  387. for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
  388. sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
  389. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  390. sunxi_gpio_set_drv(pin, 2);
  391. }
  392. } else {
  393. /* SDC1: PG0-PG5 */
  394. for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
  395. sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
  396. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  397. sunxi_gpio_set_drv(pin, 2);
  398. }
  399. }
  400. #endif
  401. break;
  402. case 2:
  403. pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
  404. #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
  405. /* SDC2: PC6-PC11 */
  406. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
  407. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  408. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  409. sunxi_gpio_set_drv(pin, 2);
  410. }
  411. #elif defined(CONFIG_MACH_SUN5I)
  412. if (pins == SUNXI_GPIO_E) {
  413. /* SDC2: PE4-PE9 */
  414. for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
  415. sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
  416. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  417. sunxi_gpio_set_drv(pin, 2);
  418. }
  419. } else {
  420. /* SDC2: PC6-PC15 */
  421. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  422. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  423. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  424. sunxi_gpio_set_drv(pin, 2);
  425. }
  426. }
  427. #elif defined(CONFIG_MACH_SUN6I)
  428. if (pins == SUNXI_GPIO_A) {
  429. /* SDC2: PA9-PA14 */
  430. for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
  431. sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
  432. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  433. sunxi_gpio_set_drv(pin, 2);
  434. }
  435. } else {
  436. /* SDC2: PC6-PC15, PC24 */
  437. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  438. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  439. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  440. sunxi_gpio_set_drv(pin, 2);
  441. }
  442. sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
  443. sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
  444. sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
  445. }
  446. #elif defined(CONFIG_MACH_SUN8I_R40)
  447. /* SDC2: PC6-PC15, PC24 */
  448. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  449. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  450. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  451. sunxi_gpio_set_drv(pin, 2);
  452. }
  453. sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
  454. sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
  455. sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
  456. #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
  457. /* SDC2: PC5-PC6, PC8-PC16 */
  458. for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
  459. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  460. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  461. sunxi_gpio_set_drv(pin, 2);
  462. }
  463. for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
  464. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  465. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  466. sunxi_gpio_set_drv(pin, 2);
  467. }
  468. #elif defined(CONFIG_MACH_SUN50I_H6)
  469. /* SDC2: PC4-PC14 */
  470. for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
  471. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  472. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  473. sunxi_gpio_set_drv(pin, 2);
  474. }
  475. #elif defined(CONFIG_MACH_SUN9I)
  476. /* SDC2: PC6-PC16 */
  477. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
  478. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  479. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  480. sunxi_gpio_set_drv(pin, 2);
  481. }
  482. #endif
  483. break;
  484. case 3:
  485. pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
  486. #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
  487. defined(CONFIG_MACH_SUN8I_R40)
  488. /* SDC3: PI4-PI9 */
  489. for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
  490. sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
  491. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  492. sunxi_gpio_set_drv(pin, 2);
  493. }
  494. #elif defined(CONFIG_MACH_SUN6I)
  495. if (pins == SUNXI_GPIO_A) {
  496. /* SDC3: PA9-PA14 */
  497. for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
  498. sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
  499. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  500. sunxi_gpio_set_drv(pin, 2);
  501. }
  502. } else {
  503. /* SDC3: PC6-PC15, PC24 */
  504. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  505. sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
  506. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  507. sunxi_gpio_set_drv(pin, 2);
  508. }
  509. sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
  510. sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
  511. sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
  512. }
  513. #endif
  514. break;
  515. default:
  516. printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
  517. break;
  518. }
  519. }
  520. int board_mmc_init(struct bd_info *bis)
  521. {
  522. __maybe_unused struct mmc *mmc0, *mmc1;
  523. mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
  524. mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
  525. if (!mmc0)
  526. return -1;
  527. #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
  528. mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
  529. mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
  530. if (!mmc1)
  531. return -1;
  532. #endif
  533. return 0;
  534. }
  535. #endif
  536. #ifdef CONFIG_SPL_BUILD
  537. static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
  538. {
  539. struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
  540. if (spl == INVALID_SPL_HEADER)
  541. return;
  542. /* Promote the header version for U-Boot proper, if needed. */
  543. if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
  544. spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
  545. spl->dram_size = dram_size >> 20;
  546. }
  547. void sunxi_board_init(void)
  548. {
  549. int power_failed = 0;
  550. #ifdef CONFIG_SY8106A_POWER
  551. power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
  552. #endif
  553. #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
  554. defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
  555. defined CONFIG_AXP818_POWER
  556. power_failed = axp_init();
  557. #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
  558. defined CONFIG_AXP818_POWER
  559. power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
  560. #endif
  561. power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
  562. power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
  563. #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
  564. power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
  565. #endif
  566. #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
  567. defined CONFIG_AXP818_POWER
  568. power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
  569. #endif
  570. #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
  571. defined CONFIG_AXP818_POWER
  572. power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
  573. #endif
  574. power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
  575. #if !defined(CONFIG_AXP152_POWER)
  576. power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
  577. #endif
  578. #ifdef CONFIG_AXP209_POWER
  579. power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
  580. #endif
  581. #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
  582. defined(CONFIG_AXP818_POWER)
  583. power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
  584. power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
  585. #if !defined CONFIG_AXP809_POWER
  586. power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
  587. power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
  588. #endif
  589. power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
  590. power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
  591. power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
  592. #endif
  593. #ifdef CONFIG_AXP818_POWER
  594. power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
  595. power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
  596. power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
  597. #endif
  598. #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
  599. power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
  600. #endif
  601. #endif
  602. //printf("DRAM:");
  603. gd->ram_size = sunxi_dram_init();
  604. //printf(" %d MiB\n", (int)(gd->ram_size >> 20));
  605. if (!gd->ram_size)
  606. hang();
  607. sunxi_spl_store_dram_size(gd->ram_size);
  608. /*
  609. * Only clock up the CPU to full speed if we are reasonably
  610. * assured it's being powered with suitable core voltage
  611. */
  612. if (!power_failed)
  613. clock_set_pll1(CONFIG_SYS_CLK_FREQ);
  614. else
  615. printf("Failed to set core voltage! Can't set CPU frequency\n");
  616. }
  617. #endif
  618. #ifdef CONFIG_USB_GADGET
  619. int g_dnl_board_usb_cable_connected(void)
  620. {
  621. struct udevice *dev;
  622. struct phy phy;
  623. int ret;
  624. ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
  625. if (ret) {
  626. pr_err("%s: Cannot find USB device\n", __func__);
  627. return ret;
  628. }
  629. ret = generic_phy_get_by_name(dev, "usb", &phy);
  630. if (ret) {
  631. pr_err("failed to get %s USB PHY\n", dev->name);
  632. return ret;
  633. }
  634. ret = generic_phy_init(&phy);
  635. if (ret) {
  636. pr_debug("failed to init %s USB PHY\n", dev->name);
  637. return ret;
  638. }
  639. ret = sun4i_usb_phy_vbus_detect(&phy);
  640. if (ret == 1) {
  641. pr_err("A charger is plugged into the OTG\n");
  642. return -ENODEV;
  643. }
  644. return ret;
  645. }
  646. #endif
  647. #ifdef CONFIG_SERIAL_TAG
  648. void get_board_serial(struct tag_serialnr *serialnr)
  649. {
  650. char *serial_string;
  651. unsigned long long serial;
  652. serial_string = env_get("serial#");
  653. if (serial_string) {
  654. serial = simple_strtoull(serial_string, NULL, 16);
  655. serialnr->high = (unsigned int) (serial >> 32);
  656. serialnr->low = (unsigned int) (serial & 0xffffffff);
  657. } else {
  658. serialnr->high = 0;
  659. serialnr->low = 0;
  660. }
  661. }
  662. #endif
  663. /*
  664. * Check the SPL header for the "sunxi" variant. If found: parse values
  665. * that might have been passed by the loader ("fel" utility), and update
  666. * the environment accordingly.
  667. */
  668. static void parse_spl_header(const uint32_t spl_addr)
  669. {
  670. struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
  671. if (spl == INVALID_SPL_HEADER)
  672. return;
  673. if (!spl->fel_script_address)
  674. return;
  675. if (spl->fel_uEnv_length != 0) {
  676. /*
  677. * data is expected in uEnv.txt compatible format, so "env
  678. * import -t" the string(s) at fel_script_address right away.
  679. */
  680. himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
  681. spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
  682. return;
  683. }
  684. /* otherwise assume .scr format (mkimage-type script) */
  685. env_set_hex("fel_scriptaddr", spl->fel_script_address);
  686. }
  687. /*
  688. * Note this function gets called multiple times.
  689. * It must not make any changes to env variables which already exist.
  690. */
  691. static void setup_environment(const void *fdt)
  692. {
  693. char serial_string[17] = { 0 };
  694. unsigned int sid[4];
  695. uint8_t mac_addr[6];
  696. char ethaddr[16];
  697. int i, ret;
  698. ret = sunxi_get_sid(sid);
  699. if (ret == 0 && sid[0] != 0) {
  700. /*
  701. * The single words 1 - 3 of the SID have quite a few bits
  702. * which are the same on many models, so we take a crc32
  703. * of all 3 words, to get a more unique value.
  704. *
  705. * Note we only do this on newer SoCs as we cannot change
  706. * the algorithm on older SoCs since those have been using
  707. * fixed mac-addresses based on only using word 3 for a
  708. * long time and changing a fixed mac-address with an
  709. * u-boot update is not good.
  710. */
  711. #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
  712. !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
  713. !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
  714. sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
  715. #endif
  716. /* Ensure the NIC specific bytes of the mac are not all 0 */
  717. if ((sid[3] & 0xffffff) == 0)
  718. sid[3] |= 0x800000;
  719. #if defined(CONFIG_CMD_NET)
  720. for (i = 0; i < 4; i++) {
  721. sprintf(ethaddr, "ethernet%d", i);
  722. if (!fdt_get_alias(fdt, ethaddr))
  723. continue;
  724. if (i == 0)
  725. strcpy(ethaddr, "ethaddr");
  726. else
  727. sprintf(ethaddr, "eth%daddr", i);
  728. if (env_get(ethaddr))
  729. continue;
  730. /* Non OUI / registered MAC address */
  731. mac_addr[0] = (i << 4) | 0x02;
  732. mac_addr[1] = (sid[0] >> 0) & 0xff;
  733. mac_addr[2] = (sid[3] >> 24) & 0xff;
  734. mac_addr[3] = (sid[3] >> 16) & 0xff;
  735. mac_addr[4] = (sid[3] >> 8) & 0xff;
  736. mac_addr[5] = (sid[3] >> 0) & 0xff;
  737. eth_env_set_enetaddr(ethaddr, mac_addr);
  738. }
  739. #endif
  740. if (!env_get("serial#")) {
  741. snprintf(serial_string, sizeof(serial_string),
  742. "%08x%08x", sid[0], sid[3]);
  743. env_set("serial#", serial_string);
  744. }
  745. }
  746. }
  747. int misc_init_r(void)
  748. {
  749. uint boot;
  750. env_set("fel_booted", NULL);
  751. env_set("fel_scriptaddr", NULL);
  752. env_set("mmc_bootdev", NULL);
  753. boot = sunxi_get_boot_device();
  754. /* determine if we are running in FEL mode */
  755. if (boot == BOOT_DEVICE_BOARD) {
  756. env_set("fel_booted", "1");
  757. parse_spl_header(SPL_ADDR);
  758. /* or if we booted from MMC, and which one */
  759. } else if (boot == BOOT_DEVICE_MMC1) {
  760. env_set("mmc_bootdev", "0");
  761. } else if (boot == BOOT_DEVICE_MMC2) {
  762. env_set("mmc_bootdev", "1");
  763. }
  764. setup_environment(gd->fdt_blob);
  765. #ifdef CONFIG_USB_ETHER
  766. usb_ether_init();
  767. #endif
  768. return 0;
  769. }
  770. int ft_board_setup(void *blob, struct bd_info *bd)
  771. {
  772. int __maybe_unused r;
  773. /*
  774. * Call setup_environment again in case the boot fdt has
  775. * ethernet aliases the u-boot copy does not have.
  776. */
  777. setup_environment(blob);
  778. #ifdef CONFIG_VIDEO_DT_SIMPLEFB
  779. r = sunxi_simplefb_setup(blob);
  780. if (r)
  781. return r;
  782. #endif
  783. return 0;
  784. }
  785. #ifdef CONFIG_SPL_LOAD_FIT
  786. int board_fit_config_name_match(const char *name)
  787. {
  788. struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
  789. const char *cmp_str = (const char *)spl;
  790. /* Check if there is a DT name stored in the SPL header and use that. */
  791. if (spl != INVALID_SPL_HEADER && spl->dt_name_offset) {
  792. cmp_str += spl->dt_name_offset;
  793. } else {
  794. #ifdef CONFIG_DEFAULT_DEVICE_TREE
  795. cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
  796. #else
  797. return 0;
  798. #endif
  799. };
  800. #ifdef CONFIG_PINE64_DT_SELECTION
  801. /* Differentiate the two Pine64 board DTs by their DRAM size. */
  802. if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
  803. if ((gd->ram_size > 512 * 1024 * 1024))
  804. return !strstr(name, "plus");
  805. else
  806. return !!strstr(name, "plus");
  807. } else {
  808. return strcmp(name, cmp_str);
  809. }
  810. #endif
  811. return strcmp(name, cmp_str);
  812. }
  813. #endif