qemu-ppce500.c 7.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007,2009-2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <cpu_func.h>
  8. #include <env.h>
  9. #include <init.h>
  10. #include <pci.h>
  11. #include <time.h>
  12. #include <asm/processor.h>
  13. #include <asm/mmu.h>
  14. #include <asm/fsl_pci.h>
  15. #include <asm/io.h>
  16. #include <linux/libfdt.h>
  17. #include <fdt_support.h>
  18. #include <netdev.h>
  19. #include <fdtdec.h>
  20. #include <errno.h>
  21. #include <malloc.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. static void *get_fdt_virt(void)
  24. {
  25. return (void *)CONFIG_SYS_TMPVIRT;
  26. }
  27. static uint64_t get_fdt_phys(void)
  28. {
  29. return (uint64_t)(uintptr_t)gd->fdt_blob;
  30. }
  31. static void map_fdt_as(int esel)
  32. {
  33. u32 mas0, mas1, mas2, mas3, mas7;
  34. uint64_t fdt_phys = get_fdt_phys();
  35. unsigned long fdt_phys_tlb = fdt_phys & ~0xffffful;
  36. unsigned long fdt_virt_tlb = (ulong)get_fdt_virt() & ~0xffffful;
  37. mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(esel);
  38. mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
  39. mas2 = FSL_BOOKE_MAS2(fdt_virt_tlb, 0);
  40. mas3 = FSL_BOOKE_MAS3(fdt_phys_tlb, 0, MAS3_SW|MAS3_SR);
  41. mas7 = FSL_BOOKE_MAS7(fdt_phys_tlb);
  42. write_tlb(mas0, mas1, mas2, mas3, mas7);
  43. }
  44. uint64_t get_phys_ccsrbar_addr_early(void)
  45. {
  46. void *fdt = get_fdt_virt();
  47. uint64_t r;
  48. int size, node;
  49. u32 naddr;
  50. const fdt32_t *prop;
  51. /*
  52. * To be able to read the FDT we need to create a temporary TLB
  53. * map for it.
  54. */
  55. map_fdt_as(10);
  56. node = fdt_path_offset(fdt, "/soc");
  57. naddr = fdt_address_cells(fdt, node);
  58. prop = fdt_getprop(fdt, node, "ranges", &size);
  59. r = fdt_translate_address(fdt, node, prop + naddr);
  60. disable_tlb(10);
  61. return r;
  62. }
  63. int board_early_init_f(void)
  64. {
  65. return 0;
  66. }
  67. int checkboard(void)
  68. {
  69. return 0;
  70. }
  71. static int pci_map_region(void *fdt, int pci_node, int range_id,
  72. phys_size_t *ppaddr, pci_addr_t *pvaddr,
  73. pci_size_t *psize, ulong *pmap_addr)
  74. {
  75. uint64_t addr;
  76. uint64_t size;
  77. ulong map_addr;
  78. int r;
  79. r = fdt_read_range(fdt, pci_node, range_id, NULL, &addr, &size);
  80. if (r)
  81. return r;
  82. if (ppaddr)
  83. *ppaddr = addr;
  84. if (psize)
  85. *psize = size;
  86. if (!pmap_addr)
  87. return 0;
  88. map_addr = *pmap_addr;
  89. /* Align map_addr */
  90. map_addr += size - 1;
  91. map_addr &= ~(size - 1);
  92. if (map_addr + size >= CONFIG_SYS_PCI_MAP_END)
  93. return -1;
  94. /* Map virtual memory for range */
  95. assert(!tlb_map_range(map_addr, addr, size, TLB_MAP_IO));
  96. *pmap_addr = map_addr + size;
  97. if (pvaddr)
  98. *pvaddr = map_addr;
  99. return 0;
  100. }
  101. void pci_init_board(void)
  102. {
  103. struct pci_controller *pci_hoses;
  104. void *fdt = get_fdt_virt();
  105. int pci_node = -1;
  106. int pci_num = 0;
  107. int pci_count = 0;
  108. ulong map_addr;
  109. puts("\n");
  110. /* Start MMIO and PIO range maps above RAM */
  111. map_addr = CONFIG_SYS_PCI_MAP_START;
  112. /* Count and allocate PCI buses */
  113. pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
  114. "device_type", "pci", 4);
  115. while (pci_node != -FDT_ERR_NOTFOUND) {
  116. pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
  117. "device_type", "pci", 4);
  118. pci_count++;
  119. }
  120. if (pci_count) {
  121. pci_hoses = malloc(sizeof(struct pci_controller) * pci_count);
  122. } else {
  123. printf("PCI: disabled\n\n");
  124. return;
  125. }
  126. /* Spawn PCI buses based on device tree */
  127. pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
  128. "device_type", "pci", 4);
  129. while (pci_node != -FDT_ERR_NOTFOUND) {
  130. struct fsl_pci_info pci_info = { };
  131. const fdt32_t *reg;
  132. int r;
  133. reg = fdt_getprop(fdt, pci_node, "reg", NULL);
  134. pci_info.regs = fdt_translate_address(fdt, pci_node, reg);
  135. /* Map MMIO range */
  136. r = pci_map_region(fdt, pci_node, 0, &pci_info.mem_phys, NULL,
  137. &pci_info.mem_size, &map_addr);
  138. if (r)
  139. break;
  140. /* Map PIO range */
  141. r = pci_map_region(fdt, pci_node, 1, &pci_info.io_phys, NULL,
  142. &pci_info.io_size, &map_addr);
  143. if (r)
  144. break;
  145. /*
  146. * The PCI framework finds virtual addresses for the buses
  147. * through our address map, so tell it the physical addresses.
  148. */
  149. pci_info.mem_bus = pci_info.mem_phys;
  150. pci_info.io_bus = pci_info.io_phys;
  151. /* Instantiate */
  152. pci_info.pci_num = pci_num + 1;
  153. fsl_setup_hose(&pci_hoses[pci_num], pci_info.regs);
  154. printf("PCI: base address %lx\n", pci_info.regs);
  155. fsl_pci_init_port(&pci_info, &pci_hoses[pci_num], pci_num);
  156. /* Jump to next PCI node */
  157. pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
  158. "device_type", "pci", 4);
  159. pci_num++;
  160. }
  161. puts("\n");
  162. }
  163. int last_stage_init(void)
  164. {
  165. void *fdt = get_fdt_virt();
  166. int len = 0;
  167. const uint64_t *prop;
  168. int chosen;
  169. chosen = fdt_path_offset(fdt, "/chosen");
  170. if (chosen < 0) {
  171. printf("Couldn't find /chosen node in fdt\n");
  172. return -EIO;
  173. }
  174. /* -kernel boot */
  175. prop = fdt_getprop(fdt, chosen, "qemu,boot-kernel", &len);
  176. if (prop && (len >= 8))
  177. env_set_hex("qemu_kernel_addr", *prop);
  178. /* Give the user a variable for the host fdt */
  179. env_set_hex("fdt_addr_r", (ulong)fdt);
  180. return 0;
  181. }
  182. static uint64_t get_linear_ram_size(void)
  183. {
  184. void *fdt = get_fdt_virt();
  185. const void *prop;
  186. int memory;
  187. int len;
  188. memory = fdt_path_offset(fdt, "/memory");
  189. prop = fdt_getprop(fdt, memory, "reg", &len);
  190. if (prop && len >= 16)
  191. return *(uint64_t *)(prop+8);
  192. panic("Couldn't determine RAM size");
  193. }
  194. int board_eth_init(bd_t *bis)
  195. {
  196. return pci_eth_init(bis);
  197. }
  198. #if defined(CONFIG_OF_BOARD_SETUP)
  199. int ft_board_setup(void *blob, bd_t *bd)
  200. {
  201. FT_FSL_PCI_SETUP;
  202. return 0;
  203. }
  204. #endif
  205. void print_laws(void)
  206. {
  207. /* We don't emulate LAWs yet */
  208. }
  209. phys_size_t fixed_sdram(void)
  210. {
  211. return get_linear_ram_size();
  212. }
  213. phys_size_t fsl_ddr_sdram_size(void)
  214. {
  215. return get_linear_ram_size();
  216. }
  217. void init_tlbs(void)
  218. {
  219. phys_size_t ram_size;
  220. /*
  221. * Create a temporary AS=1 map for the fdt
  222. *
  223. * We use ESEL=0 here to overwrite the previous AS=0 map for ourselves
  224. * which was only 4k big. This way we don't have to clear any other maps.
  225. */
  226. map_fdt_as(0);
  227. /* Fetch RAM size from the fdt */
  228. ram_size = get_linear_ram_size();
  229. /* And remove our fdt map again */
  230. disable_tlb(0);
  231. /* Create an internal map of manually created TLB maps */
  232. init_used_tlb_cams();
  233. /* Create a dynamic AS=0 CCSRBAR mapping */
  234. assert(!tlb_map_range(CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  235. 1024 * 1024, TLB_MAP_IO));
  236. /* Create a RAM map that spans all accessible RAM */
  237. setup_ddr_tlbs(ram_size >> 20);
  238. /* Create a map for the TLB */
  239. assert(!tlb_map_range((ulong)get_fdt_virt(), get_fdt_phys(),
  240. 1024 * 1024, TLB_MAP_RAM));
  241. }
  242. void init_laws(void)
  243. {
  244. /* We don't emulate LAWs yet */
  245. }
  246. static uint32_t get_cpu_freq(void)
  247. {
  248. void *fdt = get_fdt_virt();
  249. int cpus_node = fdt_path_offset(fdt, "/cpus");
  250. int cpu_node = fdt_first_subnode(fdt, cpus_node);
  251. const char *prop = "clock-frequency";
  252. return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0);
  253. }
  254. void get_sys_info(sys_info_t *sys_info)
  255. {
  256. int freq = get_cpu_freq();
  257. memset(sys_info, 0, sizeof(sys_info_t));
  258. sys_info->freq_systembus = freq;
  259. sys_info->freq_ddrbus = freq;
  260. sys_info->freq_processor[0] = freq;
  261. }
  262. int get_clocks(void)
  263. {
  264. sys_info_t sys_info;
  265. get_sys_info(&sys_info);
  266. gd->cpu_clk = sys_info.freq_processor[0];
  267. gd->bus_clk = sys_info.freq_systembus;
  268. gd->mem_clk = sys_info.freq_ddrbus;
  269. gd->arch.lbc_clk = sys_info.freq_ddrbus;
  270. return 0;
  271. }
  272. unsigned long get_tbclk(void)
  273. {
  274. void *fdt = get_fdt_virt();
  275. int cpus_node = fdt_path_offset(fdt, "/cpus");
  276. int cpu_node = fdt_first_subnode(fdt, cpus_node);
  277. const char *prop = "timebase-frequency";
  278. return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0);
  279. }
  280. /********************************************
  281. * get_bus_freq
  282. * return system bus freq in Hz
  283. *********************************************/
  284. ulong get_bus_freq(ulong dummy)
  285. {
  286. sys_info_t sys_info;
  287. get_sys_info(&sys_info);
  288. return sys_info.freq_systembus;
  289. }
  290. /*
  291. * Return the number of cores on this SOC.
  292. */
  293. int cpu_numcores(void)
  294. {
  295. /*
  296. * The QEMU u-boot target only needs to drive the first core,
  297. * spinning and device tree nodes get driven by QEMU itself
  298. */
  299. return 1;
  300. }
  301. /*
  302. * Return a 32-bit mask indicating which cores are present on this SOC.
  303. */
  304. u32 cpu_mask(void)
  305. {
  306. return (1 << cpu_numcores()) - 1;
  307. }