interrupts.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000-2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. #include <common.h>
  7. #include <irq_func.h>
  8. #include <mpc8xx.h>
  9. #include <mpc8xx_irq.h>
  10. #include <time.h>
  11. #include <asm/cpm_8xx.h>
  12. #include <asm/processor.h>
  13. #include <asm/io.h>
  14. /************************************************************************/
  15. /*
  16. * CPM interrupt vector functions.
  17. */
  18. struct interrupt_action {
  19. interrupt_handler_t *handler;
  20. void *arg;
  21. };
  22. static struct interrupt_action cpm_vecs[CPMVEC_NR];
  23. static struct interrupt_action irq_vecs[NR_IRQS];
  24. static void cpm_interrupt_init(void);
  25. static void cpm_interrupt(void *regs);
  26. /************************************************************************/
  27. void interrupt_init_cpu(unsigned *decrementer_count)
  28. {
  29. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  30. *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
  31. /* disable all interrupts */
  32. out_be32(&immr->im_siu_conf.sc_simask, 0);
  33. /* Configure CPM interrupts */
  34. cpm_interrupt_init();
  35. }
  36. /************************************************************************/
  37. /*
  38. * Handle external interrupts
  39. */
  40. void external_interrupt(struct pt_regs *regs)
  41. {
  42. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  43. int irq;
  44. ulong simask;
  45. ulong vec, v_bit;
  46. /*
  47. * read the SIVEC register and shift the bits down
  48. * to get the irq number
  49. */
  50. vec = in_be32(&immr->im_siu_conf.sc_sivec);
  51. irq = vec >> 26;
  52. v_bit = 0x80000000UL >> irq;
  53. /*
  54. * Read Interrupt Mask Register and Mask Interrupts
  55. */
  56. simask = in_be32(&immr->im_siu_conf.sc_simask);
  57. clrbits_be32(&immr->im_siu_conf.sc_simask, 0xFFFF0000 >> irq);
  58. if (!(irq & 0x1)) { /* External Interrupt ? */
  59. ulong siel;
  60. /*
  61. * Read Interrupt Edge/Level Register
  62. */
  63. siel = in_be32(&immr->im_siu_conf.sc_siel);
  64. if (siel & v_bit) { /* edge triggered interrupt ? */
  65. /*
  66. * Rewrite SIPEND Register to clear interrupt
  67. */
  68. out_be32(&immr->im_siu_conf.sc_sipend, v_bit);
  69. }
  70. }
  71. if (irq_vecs[irq].handler != NULL) {
  72. irq_vecs[irq].handler(irq_vecs[irq].arg);
  73. } else {
  74. printf("\nBogus External Interrupt IRQ %d Vector %ld\n",
  75. irq, vec);
  76. /* turn off the bogus interrupt to avoid it from now */
  77. simask &= ~v_bit;
  78. }
  79. /*
  80. * Re-Enable old Interrupt Mask
  81. */
  82. out_be32(&immr->im_siu_conf.sc_simask, simask);
  83. }
  84. /************************************************************************/
  85. /*
  86. * CPM interrupt handler
  87. */
  88. static void cpm_interrupt(void *regs)
  89. {
  90. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  91. uint vec;
  92. /*
  93. * Get the vector by setting the ACK bit
  94. * and then reading the register.
  95. */
  96. out_be16(&immr->im_cpic.cpic_civr, 1);
  97. vec = in_be16(&immr->im_cpic.cpic_civr);
  98. vec >>= 11;
  99. if (cpm_vecs[vec].handler != NULL) {
  100. (*cpm_vecs[vec].handler) (cpm_vecs[vec].arg);
  101. } else {
  102. clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
  103. printf("Masking bogus CPM interrupt vector 0x%x\n", vec);
  104. }
  105. /*
  106. * After servicing the interrupt,
  107. * we have to remove the status indicator.
  108. */
  109. setbits_be32(&immr->im_cpic.cpic_cisr, 1 << vec);
  110. }
  111. /*
  112. * The CPM can generate the error interrupt when there is a race
  113. * condition between generating and masking interrupts. All we have
  114. * to do is ACK it and return. This is a no-op function so we don't
  115. * need any special tests in the interrupt handler.
  116. */
  117. static void cpm_error_interrupt(void *dummy)
  118. {
  119. }
  120. /************************************************************************/
  121. /*
  122. * Install and free an interrupt handler
  123. */
  124. void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
  125. {
  126. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  127. if ((vec & CPMVEC_OFFSET) != 0) {
  128. /* CPM interrupt */
  129. vec &= 0xffff;
  130. if (cpm_vecs[vec].handler != NULL)
  131. printf("CPM interrupt 0x%x replacing 0x%x\n",
  132. (uint)handler, (uint)cpm_vecs[vec].handler);
  133. cpm_vecs[vec].handler = handler;
  134. cpm_vecs[vec].arg = arg;
  135. setbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
  136. } else {
  137. /* SIU interrupt */
  138. if (irq_vecs[vec].handler != NULL)
  139. printf("SIU interrupt %d 0x%x replacing 0x%x\n",
  140. vec, (uint)handler, (uint)cpm_vecs[vec].handler);
  141. irq_vecs[vec].handler = handler;
  142. irq_vecs[vec].arg = arg;
  143. setbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
  144. }
  145. }
  146. void irq_free_handler(int vec)
  147. {
  148. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  149. if ((vec & CPMVEC_OFFSET) != 0) {
  150. /* CPM interrupt */
  151. vec &= 0xffff;
  152. clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
  153. cpm_vecs[vec].handler = NULL;
  154. cpm_vecs[vec].arg = NULL;
  155. } else {
  156. /* SIU interrupt */
  157. clrbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
  158. irq_vecs[vec].handler = NULL;
  159. irq_vecs[vec].arg = NULL;
  160. }
  161. }
  162. /************************************************************************/
  163. static void cpm_interrupt_init(void)
  164. {
  165. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  166. uint cicr;
  167. /*
  168. * Initialize the CPM interrupt controller.
  169. */
  170. cicr = CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1 |
  171. ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK;
  172. out_be32(&immr->im_cpic.cpic_cicr, cicr);
  173. out_be32(&immr->im_cpic.cpic_cimr, 0);
  174. /*
  175. * Install the error handler.
  176. */
  177. irq_install_handler(CPMVEC_ERROR, cpm_error_interrupt, NULL);
  178. setbits_be32(&immr->im_cpic.cpic_cicr, CICR_IEN);
  179. /*
  180. * Install the cpm interrupt handler
  181. */
  182. irq_install_handler(CPM_INTERRUPT, cpm_interrupt, NULL);
  183. }
  184. /************************************************************************/
  185. /*
  186. * timer_interrupt - gets called when the decrementer overflows,
  187. * with interrupts disabled.
  188. * Trivial implementation - no need to be really accurate.
  189. */
  190. void timer_interrupt_cpu(struct pt_regs *regs)
  191. {
  192. immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
  193. /* Reset Timer Expired and Timers Interrupt Status */
  194. out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
  195. __asm__ ("nop");
  196. /*
  197. Clear TEXPS (and TMIST on older chips). SPLSS (on older
  198. chips) is cleared too.
  199. Bitwise OR is a read-modify-write operation so ALL bits
  200. which are cleared by writing `1' would be cleared by
  201. operations like
  202. immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS;
  203. The same can be achieved by simple writing of the PLPRCR
  204. to itself. If a bit value should be preserved, read the
  205. register, ZERO the bit and write, not OR, the result back.
  206. */
  207. setbits_be32(&immr->im_clkrst.car_plprcr, 0);
  208. }
  209. /************************************************************************/