cpu.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000-2002
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. /*
  7. * m8xx.c
  8. *
  9. * CPU specific code
  10. *
  11. * written or collected and sometimes rewritten by
  12. * Magnus Damm <damm@bitsmart.com>
  13. *
  14. * minor modifications by
  15. * Wolfgang Denk <wd@denx.de>
  16. */
  17. #include <common.h>
  18. #include <cpu_func.h>
  19. #include <time.h>
  20. #include <vsprintf.h>
  21. #include <watchdog.h>
  22. #include <command.h>
  23. #include <mpc8xx.h>
  24. #include <netdev.h>
  25. #include <asm/cache.h>
  26. #include <asm/cpm_8xx.h>
  27. #include <linux/compiler.h>
  28. #include <asm/io.h>
  29. #if defined(CONFIG_OF_LIBFDT)
  30. #include <linux/libfdt.h>
  31. #include <fdt_support.h>
  32. #endif
  33. DECLARE_GLOBAL_DATA_PTR;
  34. /* ------------------------------------------------------------------------- */
  35. /* L1 i-cache */
  36. int checkicache(void)
  37. {
  38. immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
  39. memctl8xx_t __iomem *memctl = &immap->im_memctl;
  40. u32 cacheon = rd_ic_cst() & IDC_ENABLED;
  41. /* probe in flash memoryarea */
  42. u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
  43. u32 m;
  44. u32 lines = -1;
  45. wr_ic_cst(IDC_UNALL);
  46. wr_ic_cst(IDC_INVALL);
  47. wr_ic_cst(IDC_DISABLE);
  48. __asm__ volatile ("isync");
  49. while (!((m = rd_ic_cst()) & IDC_CERR2)) {
  50. wr_ic_adr(k);
  51. wr_ic_cst(IDC_LDLCK);
  52. __asm__ volatile ("isync");
  53. lines++;
  54. k += 0x10; /* the number of bytes in a cacheline */
  55. }
  56. wr_ic_cst(IDC_UNALL);
  57. wr_ic_cst(IDC_INVALL);
  58. if (cacheon)
  59. wr_ic_cst(IDC_ENABLE);
  60. else
  61. wr_ic_cst(IDC_DISABLE);
  62. __asm__ volatile ("isync");
  63. return lines << 4;
  64. };
  65. /* ------------------------------------------------------------------------- */
  66. /* L1 d-cache */
  67. /* call with cache disabled */
  68. static int checkdcache(void)
  69. {
  70. immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
  71. memctl8xx_t __iomem *memctl = &immap->im_memctl;
  72. u32 cacheon = rd_dc_cst() & IDC_ENABLED;
  73. /* probe in flash memoryarea */
  74. u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
  75. u32 m;
  76. u32 lines = -1;
  77. wr_dc_cst(IDC_UNALL);
  78. wr_dc_cst(IDC_INVALL);
  79. wr_dc_cst(IDC_DISABLE);
  80. while (!((m = rd_dc_cst()) & IDC_CERR2)) {
  81. wr_dc_adr(k);
  82. wr_dc_cst(IDC_LDLCK);
  83. lines++;
  84. k += 0x10; /* the number of bytes in a cacheline */
  85. }
  86. wr_dc_cst(IDC_UNALL);
  87. wr_dc_cst(IDC_INVALL);
  88. if (cacheon)
  89. wr_dc_cst(IDC_ENABLE);
  90. else
  91. wr_dc_cst(IDC_DISABLE);
  92. return lines << 4;
  93. };
  94. static int check_CPU(long clock, uint pvr, uint immr)
  95. {
  96. immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
  97. uint k;
  98. char buf[32];
  99. /* the highest 16 bits should be 0x0050 for a 860 */
  100. if (PVR_VER(pvr) != PVR_VER(PVR_8xx))
  101. return -1;
  102. k = (immr << 16) |
  103. in_be16(&immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]);
  104. /*
  105. * Some boards use sockets so different CPUs can be used.
  106. * We have to check chip version in run time.
  107. */
  108. switch (k) {
  109. /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
  110. case 0x08010004: /* Rev. A.0 */
  111. printf("MPC866xxxZPnnA");
  112. break;
  113. case 0x08000003: /* Rev. 0.3 */
  114. printf("MPC866xxxZPnn");
  115. break;
  116. case 0x09000000: /* 870/875/880/885 */
  117. puts("MPC885ZPnn");
  118. break;
  119. default:
  120. printf("unknown MPC86x (0x%08x)", k);
  121. break;
  122. }
  123. printf(" at %s MHz: ", strmhz(buf, clock));
  124. print_size(checkicache(), " I-Cache ");
  125. print_size(checkdcache(), " D-Cache");
  126. /* do we have a FEC (860T/P or 852/859/866/885)? */
  127. out_be32(&immap->im_cpm.cp_fec.fec_addr_low, 0x12345678);
  128. if (in_be32(&immap->im_cpm.cp_fec.fec_addr_low) == 0x12345678)
  129. printf(" FEC present");
  130. putc('\n');
  131. return 0;
  132. }
  133. /* ------------------------------------------------------------------------- */
  134. int checkcpu(void)
  135. {
  136. ulong clock = gd->cpu_clk;
  137. uint immr = get_immr(); /* Return full IMMR contents */
  138. uint pvr = get_pvr();
  139. puts("CPU: ");
  140. return check_CPU(clock, pvr, immr);
  141. }
  142. /* ------------------------------------------------------------------------- */
  143. void upmconfig(uint upm, uint *table, uint size)
  144. {
  145. uint i;
  146. uint addr = 0;
  147. immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
  148. memctl8xx_t __iomem *memctl = &immap->im_memctl;
  149. for (i = 0; i < size; i++) {
  150. out_be32(&memctl->memc_mdr, table[i]); /* (16-15) */
  151. out_be32(&memctl->memc_mcr, addr | upm); /* (16-16) */
  152. addr++;
  153. }
  154. }
  155. /* ------------------------------------------------------------------------- */
  156. int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  157. {
  158. ulong msr, addr;
  159. immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
  160. /* Checkstop Reset enable */
  161. setbits_be32(&immap->im_clkrst.car_plprcr, PLPRCR_CSR);
  162. /* Interrupts and MMU off */
  163. __asm__ volatile ("mtspr 81, 0");
  164. __asm__ volatile ("mfmsr %0" : "=r" (msr));
  165. msr &= ~0x1030;
  166. __asm__ volatile ("mtmsr %0" : : "r" (msr));
  167. /*
  168. * Trying to execute the next instruction at a non-existing address
  169. * should cause a machine check, resulting in reset
  170. */
  171. #ifdef CONFIG_SYS_RESET_ADDRESS
  172. addr = CONFIG_SYS_RESET_ADDRESS;
  173. #else
  174. /*
  175. * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
  176. * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid address.
  177. * Better pick an address known to be invalid on your system and assign
  178. * it to CONFIG_SYS_RESET_ADDRESS.
  179. * "(ulong)-1" used to be a good choice for many systems...
  180. */
  181. addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong);
  182. #endif
  183. ((void (*)(void)) addr)();
  184. return 1;
  185. }
  186. /* ------------------------------------------------------------------------- */
  187. /*
  188. * Get timebase clock frequency (like cpu_clk in Hz)
  189. *
  190. * See sections 14.2 and 14.6 of the User's Manual
  191. */
  192. unsigned long get_tbclk(void)
  193. {
  194. immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
  195. ulong oscclk, factor, pll;
  196. if (in_be32(&immap->im_clkrst.car_sccr) & SCCR_TBS)
  197. return gd->cpu_clk / 16;
  198. pll = in_be32(&immap->im_clkrst.car_plprcr);
  199. #define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
  200. /*
  201. * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
  202. * factor is calculated as follows:
  203. *
  204. * MFN
  205. * MFI + -------
  206. * MFD + 1
  207. * factor = -----------------
  208. * (PDF + 1) * 2^S
  209. *
  210. */
  211. factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD) + 1)) /
  212. (PLPRCR_val(PDF) + 1) / (1 << PLPRCR_val(S));
  213. oscclk = gd->cpu_clk / factor;
  214. if ((in_be32(&immap->im_clkrst.car_sccr) & SCCR_RTSEL) == 0 ||
  215. factor > 2)
  216. return oscclk / 4;
  217. return oscclk / 16;
  218. }
  219. /*
  220. * Initializes on-chip ethernet controllers.
  221. * to override, implement board_eth_init()
  222. */
  223. int cpu_eth_init(bd_t *bis)
  224. {
  225. #if defined(CONFIG_MPC8XX_FEC)
  226. fec_initialize(bis);
  227. #endif
  228. return 0;
  229. }