fdt.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007-2011 Freescale Semiconductor, Inc.
  4. *
  5. * (C) Copyright 2000
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. */
  8. #include <common.h>
  9. #include <clock_legacy.h>
  10. #include <env.h>
  11. #include <time.h>
  12. #include <linux/libfdt.h>
  13. #include <fdt_support.h>
  14. #include <asm/processor.h>
  15. #include <linux/ctype.h>
  16. #include <asm/io.h>
  17. #include <asm/fsl_fdt.h>
  18. #include <asm/fsl_portals.h>
  19. #include <fsl_qbman.h>
  20. #include <hwconfig.h>
  21. #ifdef CONFIG_FSL_ESDHC
  22. #include <fsl_esdhc.h>
  23. #endif
  24. #ifdef CONFIG_SYS_DPAA_FMAN
  25. #include <fsl_fman.h>
  26. #endif
  27. DECLARE_GLOBAL_DATA_PTR;
  28. extern void ft_qe_setup(void *blob);
  29. extern void ft_fixup_num_cores(void *blob);
  30. extern void ft_srio_setup(void *blob);
  31. #ifdef CONFIG_MP
  32. #include "mp.h"
  33. void ft_fixup_cpu(void *blob, u64 memory_limit)
  34. {
  35. int off;
  36. phys_addr_t spin_tbl_addr = get_spin_phys_addr();
  37. u32 bootpg = determine_mp_bootpg(NULL);
  38. u32 id = get_my_id();
  39. const char *enable_method;
  40. #if defined(T1040_TDM_QUIRK_CCSR_BASE)
  41. int ret;
  42. int tdm_hwconfig_enabled = 0;
  43. char buffer[HWCONFIG_BUFFER_SIZE] = {0};
  44. #endif
  45. off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  46. while (off != -FDT_ERR_NOTFOUND) {
  47. u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
  48. if (reg) {
  49. u32 phys_cpu_id = thread_to_core(*reg);
  50. u64 val = phys_cpu_id * SIZE_BOOT_ENTRY + spin_tbl_addr;
  51. val = cpu_to_fdt64(val);
  52. if (*reg == id) {
  53. fdt_setprop_string(blob, off, "status",
  54. "okay");
  55. } else {
  56. fdt_setprop_string(blob, off, "status",
  57. "disabled");
  58. }
  59. if (hold_cores_in_reset(0)) {
  60. #ifdef CONFIG_FSL_CORENET
  61. /* Cores held in reset, use BRR to release */
  62. enable_method = "fsl,brr-holdoff";
  63. #else
  64. /* Cores held in reset, use EEBPCR to release */
  65. enable_method = "fsl,eebpcr-holdoff";
  66. #endif
  67. } else {
  68. /* Cores out of reset and in a spin-loop */
  69. enable_method = "spin-table";
  70. fdt_setprop(blob, off, "cpu-release-addr",
  71. &val, sizeof(val));
  72. }
  73. fdt_setprop_string(blob, off, "enable-method",
  74. enable_method);
  75. } else {
  76. printf ("cpu NULL\n");
  77. }
  78. off = fdt_node_offset_by_prop_value(blob, off,
  79. "device_type", "cpu", 4);
  80. }
  81. #if defined(T1040_TDM_QUIRK_CCSR_BASE)
  82. #define CONFIG_MEM_HOLE_16M 0x1000000
  83. /*
  84. * Extract hwconfig from environment.
  85. * Search for tdm entry in hwconfig.
  86. */
  87. ret = env_get_f("hwconfig", buffer, sizeof(buffer));
  88. if (ret > 0)
  89. tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
  90. /* Reserve the memory hole created by TDM LAW, so OSes dont use it */
  91. if (tdm_hwconfig_enabled) {
  92. off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE,
  93. CONFIG_MEM_HOLE_16M);
  94. if (off < 0)
  95. printf("Failed to reserve memory for tdm: %s\n",
  96. fdt_strerror(off));
  97. }
  98. #endif
  99. /* Reserve the boot page so OSes dont use it */
  100. if ((u64)bootpg < memory_limit) {
  101. off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
  102. if (off < 0)
  103. printf("Failed to reserve memory for bootpg: %s\n",
  104. fdt_strerror(off));
  105. }
  106. #ifndef CONFIG_MPC8xxx_DISABLE_BPTR
  107. /*
  108. * Reserve the default boot page so OSes dont use it.
  109. * The default boot page is always mapped to bootpg above using
  110. * boot page translation.
  111. */
  112. if (0xfffff000ull < memory_limit) {
  113. off = fdt_add_mem_rsv(blob, 0xfffff000ull, (u64)4096);
  114. if (off < 0) {
  115. printf("Failed to reserve memory for 0xfffff000: %s\n",
  116. fdt_strerror(off));
  117. }
  118. }
  119. #endif
  120. /* Reserve spin table page */
  121. if (spin_tbl_addr < memory_limit) {
  122. off = fdt_add_mem_rsv(blob,
  123. (spin_tbl_addr & ~0xffful), 4096);
  124. if (off < 0)
  125. printf("Failed to reserve memory for spin table: %s\n",
  126. fdt_strerror(off));
  127. }
  128. #ifdef CONFIG_DEEP_SLEEP
  129. #ifdef CONFIG_SPL_MMC_BOOT
  130. off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START,
  131. CONFIG_SYS_MMC_U_BOOT_SIZE);
  132. if (off < 0)
  133. printf("Failed to reserve memory for SD deep sleep: %s\n",
  134. fdt_strerror(off));
  135. #elif defined(CONFIG_SPL_SPI_BOOT)
  136. off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START,
  137. CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE);
  138. if (off < 0)
  139. printf("Failed to reserve memory for SPI deep sleep: %s\n",
  140. fdt_strerror(off));
  141. #endif
  142. #endif
  143. }
  144. #endif
  145. #ifdef CONFIG_SYS_FSL_CPC
  146. static inline void ft_fixup_l3cache(void *blob, int off)
  147. {
  148. u32 line_size, num_ways, size, num_sets;
  149. cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR;
  150. u32 cfg0 = in_be32(&cpc->cpccfg0);
  151. size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
  152. num_ways = CPC_CFG0_NUM_WAYS(cfg0);
  153. line_size = CPC_CFG0_LINE_SZ(cfg0);
  154. num_sets = size / (line_size * num_ways);
  155. fdt_setprop(blob, off, "cache-unified", NULL, 0);
  156. fdt_setprop_cell(blob, off, "cache-block-size", line_size);
  157. fdt_setprop_cell(blob, off, "cache-size", size);
  158. fdt_setprop_cell(blob, off, "cache-sets", num_sets);
  159. fdt_setprop_cell(blob, off, "cache-level", 3);
  160. #ifdef CONFIG_SYS_CACHE_STASHING
  161. fdt_setprop_cell(blob, off, "cache-stash-id", 1);
  162. #endif
  163. }
  164. #else
  165. #define ft_fixup_l3cache(x, y)
  166. #endif
  167. #if defined(CONFIG_L2_CACHE) || \
  168. defined(CONFIG_BACKSIDE_L2_CACHE) || \
  169. defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
  170. static inline void ft_fixup_l2cache_compatible(void *blob, int off)
  171. {
  172. int len;
  173. struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
  174. if (cpu) {
  175. char buf[40];
  176. if (isdigit(cpu->name[0])) {
  177. /* MPCxxxx, where xxxx == 4-digit number */
  178. len = sprintf(buf, "fsl,mpc%s-l2-cache-controller",
  179. cpu->name) + 1;
  180. } else {
  181. /* Pxxxx or Txxxx, where xxxx == 4-digit number */
  182. len = sprintf(buf, "fsl,%c%s-l2-cache-controller",
  183. tolower(cpu->name[0]), cpu->name + 1) + 1;
  184. }
  185. /*
  186. * append "cache" after the NULL character that the previous
  187. * sprintf wrote. This is how a device tree stores multiple
  188. * strings in a property.
  189. */
  190. len += sprintf(buf + len, "cache") + 1;
  191. fdt_setprop(blob, off, "compatible", buf, len);
  192. }
  193. }
  194. #endif
  195. #if defined(CONFIG_L2_CACHE)
  196. /* return size in kilobytes */
  197. static inline u32 l2cache_size(void)
  198. {
  199. volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
  200. volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
  201. u32 ver = SVR_SOC_VER(get_svr());
  202. switch (l2siz_field) {
  203. case 0x0:
  204. break;
  205. case 0x1:
  206. if (ver == SVR_8540 || ver == SVR_8560 ||
  207. ver == SVR_8541 || ver == SVR_8555)
  208. return 128;
  209. else
  210. return 256;
  211. break;
  212. case 0x2:
  213. if (ver == SVR_8540 || ver == SVR_8560 ||
  214. ver == SVR_8541 || ver == SVR_8555)
  215. return 256;
  216. else
  217. return 512;
  218. break;
  219. case 0x3:
  220. return 1024;
  221. break;
  222. }
  223. return 0;
  224. }
  225. static inline void ft_fixup_l2cache(void *blob)
  226. {
  227. int off;
  228. u32 *ph;
  229. const u32 line_size = 32;
  230. const u32 num_ways = 8;
  231. const u32 size = l2cache_size() * 1024;
  232. const u32 num_sets = size / (line_size * num_ways);
  233. off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  234. if (off < 0) {
  235. debug("no cpu node fount\n");
  236. return;
  237. }
  238. ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
  239. if (ph == NULL) {
  240. debug("no next-level-cache property\n");
  241. return ;
  242. }
  243. off = fdt_node_offset_by_phandle(blob, *ph);
  244. if (off < 0) {
  245. printf("%s: %s\n", __func__, fdt_strerror(off));
  246. return ;
  247. }
  248. ft_fixup_l2cache_compatible(blob, off);
  249. fdt_setprop(blob, off, "cache-unified", NULL, 0);
  250. fdt_setprop_cell(blob, off, "cache-block-size", line_size);
  251. fdt_setprop_cell(blob, off, "cache-size", size);
  252. fdt_setprop_cell(blob, off, "cache-sets", num_sets);
  253. fdt_setprop_cell(blob, off, "cache-level", 2);
  254. /* we dont bother w/L3 since no platform of this type has one */
  255. }
  256. #elif defined(CONFIG_BACKSIDE_L2_CACHE) || \
  257. defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
  258. static inline void ft_fixup_l2cache(void *blob)
  259. {
  260. int off, l2_off, l3_off = -1;
  261. u32 *ph;
  262. #ifdef CONFIG_BACKSIDE_L2_CACHE
  263. u32 l2cfg0 = mfspr(SPRN_L2CFG0);
  264. #else
  265. struct ccsr_cluster_l2 *l2cache =
  266. (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2);
  267. u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
  268. #endif
  269. u32 size, line_size, num_ways, num_sets;
  270. int has_l2 = 1;
  271. /* P2040/P2040E has no L2, so dont set any L2 props */
  272. if (SVR_SOC_VER(get_svr()) == SVR_P2040)
  273. has_l2 = 0;
  274. size = (l2cfg0 & 0x3fff) * 64 * 1024;
  275. num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
  276. line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32;
  277. num_sets = size / (line_size * num_ways);
  278. off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  279. while (off != -FDT_ERR_NOTFOUND) {
  280. ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
  281. if (ph == NULL) {
  282. debug("no next-level-cache property\n");
  283. goto next;
  284. }
  285. l2_off = fdt_node_offset_by_phandle(blob, *ph);
  286. if (l2_off < 0) {
  287. printf("%s: %s\n", __func__, fdt_strerror(off));
  288. goto next;
  289. }
  290. if (has_l2) {
  291. #ifdef CONFIG_SYS_CACHE_STASHING
  292. u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
  293. #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
  294. /* Only initialize every eighth thread */
  295. if (reg && !((*reg) % 8)) {
  296. fdt_setprop_cell(blob, l2_off, "cache-stash-id",
  297. (*reg / 4) + 32 + 1);
  298. }
  299. #else
  300. if (reg) {
  301. fdt_setprop_cell(blob, l2_off, "cache-stash-id",
  302. (*reg * 2) + 32 + 1);
  303. }
  304. #endif
  305. #endif
  306. fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
  307. fdt_setprop_cell(blob, l2_off, "cache-block-size",
  308. line_size);
  309. fdt_setprop_cell(blob, l2_off, "cache-size", size);
  310. fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
  311. fdt_setprop_cell(blob, l2_off, "cache-level", 2);
  312. ft_fixup_l2cache_compatible(blob, l2_off);
  313. }
  314. if (l3_off < 0) {
  315. ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
  316. if (ph == NULL) {
  317. debug("no next-level-cache property\n");
  318. goto next;
  319. }
  320. l3_off = *ph;
  321. }
  322. next:
  323. off = fdt_node_offset_by_prop_value(blob, off,
  324. "device_type", "cpu", 4);
  325. }
  326. if (l3_off > 0) {
  327. l3_off = fdt_node_offset_by_phandle(blob, l3_off);
  328. if (l3_off < 0) {
  329. printf("%s: %s\n", __func__, fdt_strerror(off));
  330. return ;
  331. }
  332. ft_fixup_l3cache(blob, l3_off);
  333. }
  334. }
  335. #else
  336. #define ft_fixup_l2cache(x)
  337. #endif
  338. static inline void ft_fixup_cache(void *blob)
  339. {
  340. int off;
  341. off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  342. while (off != -FDT_ERR_NOTFOUND) {
  343. u32 l1cfg0 = mfspr(SPRN_L1CFG0);
  344. u32 l1cfg1 = mfspr(SPRN_L1CFG1);
  345. u32 isize, iline_size, inum_sets, inum_ways;
  346. u32 dsize, dline_size, dnum_sets, dnum_ways;
  347. /* d-side config */
  348. dsize = (l1cfg0 & 0x7ff) * 1024;
  349. dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
  350. dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
  351. dnum_sets = dsize / (dline_size * dnum_ways);
  352. fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
  353. fdt_setprop_cell(blob, off, "d-cache-size", dsize);
  354. fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
  355. #ifdef CONFIG_SYS_CACHE_STASHING
  356. {
  357. u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
  358. if (reg)
  359. fdt_setprop_cell(blob, off, "cache-stash-id",
  360. (*reg * 2) + 32 + 0);
  361. }
  362. #endif
  363. /* i-side config */
  364. isize = (l1cfg1 & 0x7ff) * 1024;
  365. inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
  366. iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
  367. inum_sets = isize / (iline_size * inum_ways);
  368. fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
  369. fdt_setprop_cell(blob, off, "i-cache-size", isize);
  370. fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
  371. off = fdt_node_offset_by_prop_value(blob, off,
  372. "device_type", "cpu", 4);
  373. }
  374. ft_fixup_l2cache(blob);
  375. }
  376. void fdt_add_enet_stashing(void *fdt)
  377. {
  378. do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
  379. do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
  380. do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
  381. do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1);
  382. do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1);
  383. do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1);
  384. }
  385. #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
  386. #ifdef CONFIG_SYS_DPAA_FMAN
  387. static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
  388. unsigned long freq)
  389. {
  390. phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS;
  391. int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
  392. if (off >= 0) {
  393. off = fdt_setprop_cell(blob, off, "clock-frequency", freq);
  394. if (off > 0)
  395. printf("WARNING enable to set clock-frequency "
  396. "for %s: %s\n", compat, fdt_strerror(off));
  397. }
  398. }
  399. #endif
  400. static void ft_fixup_dpaa_clks(void *blob)
  401. {
  402. sys_info_t sysinfo;
  403. get_sys_info(&sysinfo);
  404. #ifdef CONFIG_SYS_DPAA_FMAN
  405. ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
  406. sysinfo.freq_fman[0]);
  407. #if (CONFIG_SYS_NUM_FMAN == 2)
  408. ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
  409. sysinfo.freq_fman[1]);
  410. #endif
  411. #endif
  412. #ifdef CONFIG_SYS_DPAA_QBMAN
  413. do_fixup_by_compat_u32(blob, "fsl,qman",
  414. "clock-frequency", sysinfo.freq_qman, 1);
  415. #endif
  416. #ifdef CONFIG_SYS_DPAA_PME
  417. do_fixup_by_compat_u32(blob, "fsl,pme",
  418. "clock-frequency", sysinfo.freq_pme, 1);
  419. #endif
  420. }
  421. #else
  422. #define ft_fixup_dpaa_clks(x)
  423. #endif
  424. #ifdef CONFIG_QE
  425. static void ft_fixup_qe_snum(void *blob)
  426. {
  427. unsigned int svr;
  428. svr = mfspr(SPRN_SVR);
  429. if (SVR_SOC_VER(svr) == SVR_8569) {
  430. if(IS_SVR_REV(svr, 1, 0))
  431. do_fixup_by_compat_u32(blob, "fsl,qe",
  432. "fsl,qe-num-snums", 46, 1);
  433. else
  434. do_fixup_by_compat_u32(blob, "fsl,qe",
  435. "fsl,qe-num-snums", 76, 1);
  436. }
  437. }
  438. #endif
  439. #if defined(CONFIG_ARCH_P4080)
  440. static void fdt_fixup_usb(void *fdt)
  441. {
  442. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  443. u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
  444. int off;
  445. off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-mph");
  446. if ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) !=
  447. FSL_CORENET_RCWSR11_EC1_FM1_USB1)
  448. fdt_status_disabled(fdt, off);
  449. off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-dr");
  450. if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) !=
  451. FSL_CORENET_RCWSR11_EC2_USB2)
  452. fdt_status_disabled(fdt, off);
  453. }
  454. #else
  455. #define fdt_fixup_usb(x)
  456. #endif
  457. #if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) || \
  458. defined(CONFIG_ARCH_T4160)
  459. void fdt_fixup_dma3(void *blob)
  460. {
  461. /* the 3rd DMA is not functional if SRIO2 is chosen */
  462. int nodeoff;
  463. ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  464. #define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
  465. #if defined(CONFIG_ARCH_T2080)
  466. u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
  467. FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  468. srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  469. switch (srds_prtcl_s2) {
  470. case 0x29:
  471. case 0x2d:
  472. case 0x2e:
  473. #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
  474. u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
  475. FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
  476. srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
  477. switch (srds_prtcl_s4) {
  478. case 6:
  479. case 8:
  480. case 14:
  481. case 16:
  482. #endif
  483. nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma",
  484. CONFIG_SYS_ELO3_DMA3);
  485. if (nodeoff > 0)
  486. fdt_status_disabled(blob, nodeoff);
  487. else
  488. printf("WARNING: unable to disable dma3\n");
  489. break;
  490. default:
  491. break;
  492. }
  493. }
  494. #else
  495. #define fdt_fixup_dma3(x)
  496. #endif
  497. #if defined(CONFIG_ARCH_T1040)
  498. static void fdt_fixup_l2_switch(void *blob)
  499. {
  500. uchar l2swaddr[6];
  501. int node;
  502. /* The l2switch node from device-tree has
  503. * compatible string "vitesse-9953" */
  504. node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953");
  505. if (node == -FDT_ERR_NOTFOUND)
  506. /* no l2switch node has been found */
  507. return;
  508. /* Get MAC address for the l2switch from "l2switchaddr"*/
  509. if (!eth_env_get_enetaddr("l2switchaddr", l2swaddr)) {
  510. printf("Warning: MAC address for l2switch not found\n");
  511. memset(l2swaddr, 0, sizeof(l2swaddr));
  512. }
  513. /* Add MAC address to l2switch node */
  514. fdt_setprop(blob, node, "local-mac-address", l2swaddr,
  515. sizeof(l2swaddr));
  516. }
  517. #else
  518. #define fdt_fixup_l2_switch(x)
  519. #endif
  520. void ft_cpu_setup(void *blob, bd_t *bd)
  521. {
  522. int off;
  523. int val;
  524. int len;
  525. sys_info_t sysinfo;
  526. /* delete crypto node if not on an E-processor */
  527. if (!IS_E_PROCESSOR(get_svr()))
  528. fdt_fixup_crypto_node(blob, 0);
  529. #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
  530. else {
  531. ccsr_sec_t __iomem *sec;
  532. sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
  533. fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
  534. }
  535. #endif
  536. fdt_add_enet_stashing(blob);
  537. #ifndef CONFIG_FSL_TBCLK_EXTRA_DIV
  538. #define CONFIG_FSL_TBCLK_EXTRA_DIV 1
  539. #endif
  540. do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
  541. "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV,
  542. 1);
  543. do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
  544. "bus-frequency", bd->bi_busfreq, 1);
  545. get_sys_info(&sysinfo);
  546. off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  547. while (off != -FDT_ERR_NOTFOUND) {
  548. u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len);
  549. val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]);
  550. fdt_setprop(blob, off, "clock-frequency", &val, 4);
  551. off = fdt_node_offset_by_prop_value(blob, off, "device_type",
  552. "cpu", 4);
  553. }
  554. do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
  555. "bus-frequency", bd->bi_busfreq, 1);
  556. #ifdef CONFIG_QE
  557. ft_qe_setup(blob);
  558. ft_fixup_qe_snum(blob);
  559. #endif
  560. #ifdef CONFIG_SYS_DPAA_FMAN
  561. fdt_fixup_fman_firmware(blob);
  562. #endif
  563. #ifdef CONFIG_SYS_NS16550
  564. do_fixup_by_compat_u32(blob, "ns16550",
  565. "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
  566. #endif
  567. #ifdef CONFIG_CPM2
  568. do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
  569. "current-speed", gd->baudrate, 1);
  570. do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
  571. "clock-frequency", bd->bi_brgfreq, 1);
  572. #endif
  573. #ifdef CONFIG_FSL_CORENET
  574. do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
  575. "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
  576. do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0",
  577. "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
  578. do_fixup_by_compat_u32(blob, "fsl,mpic",
  579. "clock-frequency", get_bus_freq(0)/2, 1);
  580. #else
  581. do_fixup_by_compat_u32(blob, "fsl,mpic",
  582. "clock-frequency", get_bus_freq(0), 1);
  583. #endif
  584. fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
  585. #ifdef CONFIG_MP
  586. ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
  587. ft_fixup_num_cores(blob);
  588. #endif
  589. ft_fixup_cache(blob);
  590. #if defined(CONFIG_FSL_ESDHC)
  591. fdt_fixup_esdhc(blob, bd);
  592. #endif
  593. ft_fixup_dpaa_clks(blob);
  594. #if defined(CONFIG_SYS_BMAN_MEM_PHYS)
  595. fdt_portal(blob, "fsl,bman-portal", "bman-portals",
  596. (u64)CONFIG_SYS_BMAN_MEM_PHYS,
  597. CONFIG_SYS_BMAN_MEM_SIZE);
  598. fdt_fixup_bportals(blob);
  599. #endif
  600. #if defined(CONFIG_SYS_QMAN_MEM_PHYS)
  601. fdt_portal(blob, "fsl,qman-portal", "qman-portals",
  602. (u64)CONFIG_SYS_QMAN_MEM_PHYS,
  603. CONFIG_SYS_QMAN_MEM_SIZE);
  604. fdt_fixup_qportals(blob);
  605. #endif
  606. #ifdef CONFIG_SYS_SRIO
  607. ft_srio_setup(blob);
  608. #endif
  609. /*
  610. * system-clock = CCB clock/2
  611. * Here gd->bus_clk = CCB clock
  612. * We are using the system clock as 1588 Timer reference
  613. * clock source select
  614. */
  615. do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer",
  616. "timer-frequency", gd->bus_clk/2, 1);
  617. /*
  618. * clock-freq should change to clock-frequency and
  619. * flexcan-v1.0 should change to p1010-flexcan respectively
  620. * in the future.
  621. */
  622. do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
  623. "clock_freq", gd->bus_clk/2, 1);
  624. do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
  625. "clock-frequency", gd->bus_clk/2, 1);
  626. do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan",
  627. "clock-frequency", gd->bus_clk/2, 1);
  628. fdt_fixup_usb(blob);
  629. fdt_fixup_l2_switch(blob);
  630. fdt_fixup_dma3(blob);
  631. }
  632. /*
  633. * For some CCSR devices, we only have the virtual address, not the physical
  634. * address. This is because we map CCSR as a whole, so we typically don't need
  635. * a macro for the physical address of any device within CCSR. In this case,
  636. * we calculate the physical address of that device using it's the difference
  637. * between the virtual address of the device and the virtual address of the
  638. * beginning of CCSR.
  639. */
  640. #define CCSR_VIRT_TO_PHYS(x) \
  641. (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
  642. static void msg(const char *name, uint64_t uaddr, uint64_t daddr)
  643. {
  644. printf("Warning: U-Boot configured %s at address %llx,\n"
  645. "but the device tree has it at %llx\n", name, uaddr, daddr);
  646. }
  647. /*
  648. * Verify the device tree
  649. *
  650. * This function compares several CONFIG_xxx macros that contain physical
  651. * addresses with the corresponding nodes in the device tree, to see if
  652. * the physical addresses are all correct. For example, if
  653. * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address
  654. * of the first UART. We convert this to a physical address and compare
  655. * that with the physical address of the first ns16550-compatible node
  656. * in the device tree. If they don't match, then we display a warning.
  657. *
  658. * Returns 1 on success, 0 on failure
  659. */
  660. int ft_verify_fdt(void *fdt)
  661. {
  662. uint64_t addr = 0;
  663. int aliases;
  664. int off;
  665. /* First check the CCSR base address */
  666. off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4);
  667. if (off > 0) {
  668. int size;
  669. u32 naddr;
  670. const fdt32_t *prop;
  671. naddr = fdt_address_cells(fdt, off);
  672. prop = fdt_getprop(fdt, off, "ranges", &size);
  673. addr = fdt_translate_address(fdt, off, prop + naddr);
  674. }
  675. if (!addr) {
  676. printf("Warning: could not determine base CCSR address in "
  677. "device tree\n");
  678. /* No point in checking anything else */
  679. return 0;
  680. }
  681. if (addr != CONFIG_SYS_CCSRBAR_PHYS) {
  682. msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr);
  683. /* No point in checking anything else */
  684. return 0;
  685. }
  686. /*
  687. * Check some nodes via aliases. We assume that U-Boot and the device
  688. * tree enumerate the devices equally. E.g. the first serial port in
  689. * U-Boot is the same as "serial0" in the device tree.
  690. */
  691. aliases = fdt_path_offset(fdt, "/aliases");
  692. if (aliases > 0) {
  693. #ifdef CONFIG_SYS_NS16550_COM1
  694. if (!fdt_verify_alias_address(fdt, aliases, "serial0",
  695. CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1)))
  696. return 0;
  697. #endif
  698. #ifdef CONFIG_SYS_NS16550_COM2
  699. if (!fdt_verify_alias_address(fdt, aliases, "serial1",
  700. CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2)))
  701. return 0;
  702. #endif
  703. }
  704. /*
  705. * The localbus node is typically a root node, even though the lbc
  706. * controller is part of CCSR. If we were to put the lbc node under
  707. * the SOC node, then the 'ranges' property in the lbc node would
  708. * translate through the 'ranges' property of the parent SOC node, and
  709. * we don't want that. Since it's a separate node, it's possible for
  710. * the 'reg' property to be wrong, so check it here. For now, we
  711. * only check for "fsl,elbc" nodes.
  712. */
  713. #ifdef CONFIG_SYS_LBC_ADDR
  714. off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc");
  715. if (off > 0) {
  716. const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL);
  717. if (reg) {
  718. uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR);
  719. addr = fdt_translate_address(fdt, off, reg);
  720. if (uaddr != addr) {
  721. msg("the localbus", uaddr, addr);
  722. return 0;
  723. }
  724. }
  725. }
  726. #endif
  727. return 1;
  728. }
  729. void fdt_del_diu(void *blob)
  730. {
  731. int nodeoff = 0;
  732. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  733. "fsl,diu")) >= 0) {
  734. fdt_del_node(blob, nodeoff);
  735. }
  736. }