spl_minimal.c 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <clock_legacy.h>
  7. #include <mpc83xx.h>
  8. #include <time.h>
  9. #include "lblaw/lblaw.h"
  10. #include "elbc/elbc.h"
  11. DECLARE_GLOBAL_DATA_PTR;
  12. /*
  13. * Breathe some life into the CPU...
  14. *
  15. * Set up the memory map,
  16. * initialize a bunch of registers,
  17. * initialize the UPM's
  18. */
  19. void cpu_init_f (volatile immap_t * im)
  20. {
  21. /* Pointer is writable since we allocated a register for it */
  22. gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
  23. /* global data region was cleared in start.S */
  24. /* system performance tweaking */
  25. #ifndef CONFIG_ACR_PIPE_DEP_UNSET
  26. /* Arbiter pipeline depth */
  27. im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
  28. CONFIG_ACR_PIPE_DEP;
  29. #endif
  30. #ifndef CONFIG_ACR_RPTCNT_UNSET
  31. /* Arbiter repeat count */
  32. im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
  33. CONFIG_ACR_RPTCNT;
  34. #endif
  35. #ifdef CONFIG_SYS_SPCR_OPT
  36. /* Optimize transactions between CSB and other devices */
  37. im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
  38. (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
  39. #endif
  40. /* Enable Time Base & Decrementer (so we will have udelay()) */
  41. im->sysconf.spcr |= SPCR_TBEN;
  42. /* DDR control driver register */
  43. #ifdef CONFIG_SYS_DDRCDR
  44. im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
  45. #endif
  46. /* Output buffer impedance register */
  47. #ifdef CONFIG_SYS_OBIR
  48. im->sysconf.obir = CONFIG_SYS_OBIR;
  49. #endif
  50. /*
  51. * Memory Controller:
  52. */
  53. /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
  54. * addresses - these have to be modified later when FLASH size
  55. * has been determined
  56. */
  57. #if defined(CONFIG_SYS_NAND_BR_PRELIM) \
  58. && defined(CONFIG_SYS_NAND_OR_PRELIM) \
  59. && defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
  60. && defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
  61. set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
  62. set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
  63. im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
  64. im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
  65. #else
  66. #error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
  67. #endif
  68. }
  69. /*
  70. * Get timebase clock frequency (like cpu_clk in Hz)
  71. */
  72. unsigned long get_tbclk(void)
  73. {
  74. return (gd->bus_clk + 3L) / 4L;
  75. }
  76. void puts(const char *str)
  77. {
  78. while (*str)
  79. putc(*str++);
  80. }
  81. ulong get_bus_freq(ulong dummy)
  82. {
  83. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  84. u8 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
  85. return CONFIG_SYS_CLK_FREQ * spmf;
  86. }