cpu.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014 - 2015 Xilinx, Inc.
  4. * Michal Simek <michal.simek@xilinx.com>
  5. */
  6. #include <common.h>
  7. #include <time.h>
  8. #include <asm/arch/hardware.h>
  9. #include <asm/arch/sys_proto.h>
  10. #include <asm/armv8/mmu.h>
  11. #include <asm/io.h>
  12. #include <zynqmp_firmware.h>
  13. #define ZYNQ_SILICON_VER_MASK 0xF000
  14. #define ZYNQ_SILICON_VER_SHIFT 12
  15. DECLARE_GLOBAL_DATA_PTR;
  16. /*
  17. * Number of filled static entries and also the first empty
  18. * slot in zynqmp_mem_map.
  19. */
  20. #define ZYNQMP_MEM_MAP_USED 4
  21. #if !defined(CONFIG_ZYNQMP_NO_DDR)
  22. #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
  23. #else
  24. #define DRAM_BANKS 0
  25. #endif
  26. #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  27. #define TCM_MAP 1
  28. #else
  29. #define TCM_MAP 0
  30. #endif
  31. /* +1 is end of list which needs to be empty */
  32. #define ZYNQMP_MEM_MAP_MAX (ZYNQMP_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
  33. static struct mm_region zynqmp_mem_map[ZYNQMP_MEM_MAP_MAX] = {
  34. {
  35. .virt = 0x80000000UL,
  36. .phys = 0x80000000UL,
  37. .size = 0x70000000UL,
  38. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  39. PTE_BLOCK_NON_SHARE |
  40. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  41. }, {
  42. .virt = 0xf8000000UL,
  43. .phys = 0xf8000000UL,
  44. .size = 0x07e00000UL,
  45. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  46. PTE_BLOCK_NON_SHARE |
  47. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  48. }, {
  49. .virt = 0x400000000UL,
  50. .phys = 0x400000000UL,
  51. .size = 0x400000000UL,
  52. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  53. PTE_BLOCK_NON_SHARE |
  54. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  55. }, {
  56. .virt = 0x1000000000UL,
  57. .phys = 0x1000000000UL,
  58. .size = 0xf000000000UL,
  59. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  60. PTE_BLOCK_NON_SHARE |
  61. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  62. }
  63. };
  64. void mem_map_fill(void)
  65. {
  66. int banks = ZYNQMP_MEM_MAP_USED;
  67. #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  68. zynqmp_mem_map[banks].virt = 0xffe00000UL;
  69. zynqmp_mem_map[banks].phys = 0xffe00000UL;
  70. zynqmp_mem_map[banks].size = 0x00200000UL;
  71. zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  72. PTE_BLOCK_INNER_SHARE;
  73. banks = banks + 1;
  74. #endif
  75. #if !defined(CONFIG_ZYNQMP_NO_DDR)
  76. for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  77. /* Zero size means no more DDR that's this is end */
  78. if (!gd->bd->bi_dram[i].size)
  79. break;
  80. zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start;
  81. zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start;
  82. zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size;
  83. zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  84. PTE_BLOCK_INNER_SHARE;
  85. banks = banks + 1;
  86. }
  87. #endif
  88. }
  89. struct mm_region *mem_map = zynqmp_mem_map;
  90. u64 get_page_table_size(void)
  91. {
  92. return 0x14000;
  93. }
  94. #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)
  95. void tcm_init(u8 mode)
  96. {
  97. puts("WARNING: Initializing TCM overwrites TCM content\n");
  98. initialize_tcm(mode);
  99. memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE);
  100. }
  101. #endif
  102. #ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU
  103. int reserve_mmu(void)
  104. {
  105. tcm_init(TCM_LOCK);
  106. gd->arch.tlb_size = PGTABLE_SIZE;
  107. gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR;
  108. return 0;
  109. }
  110. #endif
  111. static unsigned int zynqmp_get_silicon_version_secure(void)
  112. {
  113. u32 ver;
  114. ver = readl(&csu_base->version);
  115. ver &= ZYNQMP_SILICON_VER_MASK;
  116. ver >>= ZYNQMP_SILICON_VER_SHIFT;
  117. return ver;
  118. }
  119. unsigned int zynqmp_get_silicon_version(void)
  120. {
  121. if (current_el() == 3)
  122. return zynqmp_get_silicon_version_secure();
  123. gd->cpu_clk = get_tbclk();
  124. switch (gd->cpu_clk) {
  125. case 50000000:
  126. return ZYNQMP_CSU_VERSION_QEMU;
  127. }
  128. return ZYNQMP_CSU_VERSION_SILICON;
  129. }
  130. static int zynqmp_mmio_rawwrite(const u32 address,
  131. const u32 mask,
  132. const u32 value)
  133. {
  134. u32 data;
  135. u32 value_local = value;
  136. int ret;
  137. ret = zynqmp_mmio_read(address, &data);
  138. if (ret)
  139. return ret;
  140. data &= ~mask;
  141. value_local &= mask;
  142. value_local |= data;
  143. writel(value_local, (ulong)address);
  144. return 0;
  145. }
  146. static int zynqmp_mmio_rawread(const u32 address, u32 *value)
  147. {
  148. *value = readl((ulong)address);
  149. return 0;
  150. }
  151. int zynqmp_mmio_write(const u32 address,
  152. const u32 mask,
  153. const u32 value)
  154. {
  155. if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3)
  156. return zynqmp_mmio_rawwrite(address, mask, value);
  157. #if defined(CONFIG_ZYNQMP_FIRMWARE)
  158. else
  159. return xilinx_pm_request(PM_MMIO_WRITE, address, mask,
  160. value, 0, NULL);
  161. #endif
  162. return -EINVAL;
  163. }
  164. int zynqmp_mmio_read(const u32 address, u32 *value)
  165. {
  166. u32 ret = -EINVAL;
  167. if (!value)
  168. return ret;
  169. if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
  170. ret = zynqmp_mmio_rawread(address, value);
  171. }
  172. #if defined(CONFIG_ZYNQMP_FIRMWARE)
  173. else {
  174. u32 ret_payload[PAYLOAD_ARG_CNT];
  175. ret = xilinx_pm_request(PM_MMIO_READ, address, 0, 0,
  176. 0, ret_payload);
  177. *value = ret_payload[1];
  178. }
  179. #endif
  180. return ret;
  181. }