timer.c 1.3 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007-2008
  4. * Stelian Pop <stelian@popies.net>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. *
  7. * (C) Copyright 2013
  8. * Bo Shen <voice.shen@atmel.com>
  9. */
  10. #include <common.h>
  11. #include <time.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/hardware.h>
  14. #include <asm/arch/at91_pit.h>
  15. #include <asm/arch/clk.h>
  16. #include <div64.h>
  17. #if !defined(CONFIG_AT91FAMILY)
  18. # error You need to define CONFIG_AT91FAMILY in your board config!
  19. #endif
  20. DECLARE_GLOBAL_DATA_PTR;
  21. /*
  22. * We're using the SAMA5D3x PITC in 32 bit mode, by
  23. * setting the 20 bit counter period to its maximum (0xfffff).
  24. * (See the relevant data sheets to understand that this really works)
  25. *
  26. * We do also mimic the typical powerpc way of incrementing
  27. * two 32 bit registers called tbl and tbu.
  28. *
  29. * Those registers increment at 1/16 the main clock rate.
  30. */
  31. #define TIMER_LOAD_VAL 0xfffff
  32. /*
  33. * Use the PITC in full 32 bit incrementing mode
  34. */
  35. int timer_init(void)
  36. {
  37. at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
  38. /* Enable PITC Clock */
  39. at91_periph_clk_enable(ATMEL_ID_PIT);
  40. /* Enable PITC */
  41. writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
  42. gd->arch.timer_rate_hz = get_pit_clk_rate() / 16;
  43. return 0;
  44. }
  45. /*
  46. * Return the number of timer ticks per second.
  47. */
  48. ulong get_tbclk(void)
  49. {
  50. return gd->arch.timer_rate_hz;
  51. }