timer.c 1.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007-2008
  4. * Stelian Pop <stelian@popies.net>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. */
  7. #include <common.h>
  8. #include <time.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/hardware.h>
  11. #include <asm/arch/at91_pit.h>
  12. #include <asm/arch/clk.h>
  13. #include <div64.h>
  14. #if !defined(CONFIG_AT91FAMILY)
  15. # error You need to define CONFIG_AT91FAMILY in your board config!
  16. #endif
  17. DECLARE_GLOBAL_DATA_PTR;
  18. /*
  19. * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
  20. * setting the 20 bit counter period to its maximum (0xfffff).
  21. * (See the relevant data sheets to understand that this really works)
  22. *
  23. * We do also mimic the typical powerpc way of incrementing
  24. * two 32 bit registers called tbl and tbu.
  25. *
  26. * Those registers increment at 1/16 the main clock rate.
  27. */
  28. #define TIMER_LOAD_VAL 0xfffff
  29. /*
  30. * Use the PITC in full 32 bit incrementing mode
  31. */
  32. int timer_init(void)
  33. {
  34. at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
  35. at91_periph_clk_enable(ATMEL_ID_SYS);
  36. /* Enable PITC */
  37. writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
  38. gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
  39. return 0;
  40. }
  41. /*
  42. * Return the number of timer ticks per second.
  43. */
  44. ulong get_tbclk(void)
  45. {
  46. return gd->arch.timer_rate_hz;
  47. }