timer.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  6. * Contributor: Mahavir Jain <mjain@marvell.com>
  7. */
  8. #include <common.h>
  9. #include <time.h>
  10. #include <asm/arch/cpu.h>
  11. #include <asm/arch/armada100.h>
  12. /*
  13. * Timer registers
  14. * Refer Section A.6 in Datasheet
  15. */
  16. struct armd1tmr_registers {
  17. u32 clk_ctrl; /* Timer clk control reg */
  18. u32 match[9]; /* Timer match registers */
  19. u32 count[3]; /* Timer count registers */
  20. u32 status[3];
  21. u32 ie[3];
  22. u32 preload[3]; /* Timer preload value */
  23. u32 preload_ctrl[3];
  24. u32 wdt_match_en;
  25. u32 wdt_match_r;
  26. u32 wdt_val;
  27. u32 wdt_sts;
  28. u32 icr[3];
  29. u32 wdt_icr;
  30. u32 cer; /* Timer count enable reg */
  31. u32 cmr;
  32. u32 ilr[3];
  33. u32 wcr;
  34. u32 wfar;
  35. u32 wsar;
  36. u32 cvwr;
  37. };
  38. #define TIMER 0 /* Use TIMER 0 */
  39. /* Each timer has 3 match registers */
  40. #define MATCH_CMP(x) ((3 * TIMER) + x)
  41. #define TIMER_LOAD_VAL 0xffffffff
  42. #define COUNT_RD_REQ 0x1
  43. DECLARE_GLOBAL_DATA_PTR;
  44. /* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
  45. /* For preventing risk of instability in reading counter value,
  46. * first set read request to register cvwr and then read same
  47. * register after it captures counter value.
  48. */
  49. ulong read_timer(void)
  50. {
  51. struct armd1tmr_registers *armd1timers =
  52. (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
  53. volatile int loop=100;
  54. writel(COUNT_RD_REQ, &armd1timers->cvwr);
  55. while (loop--);
  56. return(readl(&armd1timers->cvwr));
  57. }
  58. static ulong get_timer_masked(void)
  59. {
  60. ulong now = read_timer();
  61. if (now >= gd->arch.tbl) {
  62. /* normal mode */
  63. gd->arch.tbu += now - gd->arch.tbl;
  64. } else {
  65. /* we have an overflow ... */
  66. gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
  67. }
  68. gd->arch.tbl = now;
  69. return gd->arch.tbu;
  70. }
  71. ulong get_timer(ulong base)
  72. {
  73. return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
  74. base);
  75. }
  76. void __udelay(unsigned long usec)
  77. {
  78. ulong delayticks;
  79. ulong endtime;
  80. delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
  81. endtime = get_timer_masked() + delayticks;
  82. while (get_timer_masked() < endtime);
  83. }
  84. /*
  85. * init the Timer
  86. */
  87. int timer_init(void)
  88. {
  89. struct armd1apb1_registers *apb1clkres =
  90. (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
  91. struct armd1tmr_registers *armd1timers =
  92. (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
  93. /* Enable Timer clock at 3.25 MHZ */
  94. writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
  95. /* load value into timer */
  96. writel(0x0, &armd1timers->clk_ctrl);
  97. /* Use Timer 0 Match Resiger 0 */
  98. writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
  99. /* Preload value is 0 */
  100. writel(0x0, &armd1timers->preload[TIMER]);
  101. /* Enable match comparator 0 for Timer 0 */
  102. writel(0x1, &armd1timers->preload_ctrl[TIMER]);
  103. /* Enable timer 0 */
  104. writel(0x1, &armd1timers->cer);
  105. /* init the gd->arch.tbu and gd->arch.tbl value */
  106. gd->arch.tbl = read_timer();
  107. gd->arch.tbu = 0;
  108. return 0;
  109. }
  110. #define MPMU_APRR_WDTR (1<<4)
  111. #define TMR_WFAR 0xbaba /* WDT Register First key */
  112. #define TMP_WSAR 0xeb10 /* WDT Register Second key */
  113. /*
  114. * This function uses internal Watchdog Timer
  115. * based reset mechanism.
  116. * Steps to write watchdog registers (protected access)
  117. * 1. Write key value to TMR_WFAR reg.
  118. * 2. Write key value to TMP_WSAR reg.
  119. * 3. Perform write operation.
  120. */
  121. void reset_cpu (unsigned long ignored)
  122. {
  123. struct armd1mpmu_registers *mpmu =
  124. (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
  125. struct armd1tmr_registers *armd1timers =
  126. (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
  127. u32 val;
  128. /* negate hardware reset to the WDT after system reset */
  129. val = readl(&mpmu->aprr);
  130. val = val | MPMU_APRR_WDTR;
  131. writel(val, &mpmu->aprr);
  132. /* reset/enable WDT clock */
  133. writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
  134. readl(&mpmu->wdtpcr);
  135. writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
  136. readl(&mpmu->wdtpcr);
  137. /* clear previous WDT status */
  138. writel(TMR_WFAR, &armd1timers->wfar);
  139. writel(TMP_WSAR, &armd1timers->wsar);
  140. writel(0, &armd1timers->wdt_sts);
  141. /* set match counter */
  142. writel(TMR_WFAR, &armd1timers->wfar);
  143. writel(TMP_WSAR, &armd1timers->wsar);
  144. writel(0xf, &armd1timers->wdt_match_r);
  145. /* enable WDT reset */
  146. writel(TMR_WFAR, &armd1timers->wfar);
  147. writel(TMP_WSAR, &armd1timers->wsar);
  148. writel(0x3, &armd1timers->wdt_match_en);
  149. while(1);
  150. }
  151. /*
  152. * This function is derived from PowerPC code (read timebase as long long).
  153. * On ARM it just returns the timer value.
  154. */
  155. unsigned long long get_ticks(void)
  156. {
  157. return get_timer(0);
  158. }
  159. /*
  160. * This function is derived from PowerPC code (timebase clock frequency).
  161. * On ARM it returns the number of timer ticks per second.
  162. */
  163. ulong get_tbclk(void)
  164. {
  165. return (ulong)CONFIG_SYS_HZ;
  166. }