soc.c 26 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017-2019 NXP
  4. *
  5. * Peng Fan <peng.fan@nxp.com>
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <init.h>
  10. #include <log.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <asm/mach-imx/hab.h>
  16. #include <asm/mach-imx/boot_mode.h>
  17. #include <asm/mach-imx/syscounter.h>
  18. #include <asm/ptrace.h>
  19. #include <asm/armv8/mmu.h>
  20. #include <dm/uclass.h>
  21. #include <efi_loader.h>
  22. #include <env.h>
  23. #include <env_internal.h>
  24. #include <errno.h>
  25. #include <fdt_support.h>
  26. #include <fsl_wdog.h>
  27. #include <imx_sip.h>
  28. #include <linux/arm-smccc.h>
  29. #include <linux/bitops.h>
  30. DECLARE_GLOBAL_DATA_PTR;
  31. #if defined(CONFIG_IMX_HAB)
  32. struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
  33. .bank = 1,
  34. .word = 3,
  35. };
  36. #endif
  37. int timer_init(void)
  38. {
  39. #ifdef CONFIG_SPL_BUILD
  40. struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
  41. unsigned long freq = readl(&sctr->cntfid0);
  42. /* Update with accurate clock frequency */
  43. asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
  44. clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
  45. SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
  46. #endif
  47. gd->arch.tbl = 0;
  48. gd->arch.tbu = 0;
  49. return 0;
  50. }
  51. void enable_tzc380(void)
  52. {
  53. struct iomuxc_gpr_base_regs *gpr =
  54. (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  55. /* Enable TZASC and lock setting */
  56. setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
  57. setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
  58. if (is_imx8mm() || is_imx8mn() || is_imx8mp())
  59. setbits_le32(&gpr->gpr[10], BIT(1));
  60. /*
  61. * set Region 0 attribute to allow secure and non-secure
  62. * read/write permission. Found some masters like usb dwc3
  63. * controllers can't work with secure memory.
  64. */
  65. writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
  66. }
  67. void set_wdog_reset(struct wdog_regs *wdog)
  68. {
  69. /*
  70. * Output WDOG_B signal to reset external pmic or POR_B decided by
  71. * the board design. Without external reset, the peripherals/DDR/
  72. * PMIC are not reset, that may cause system working abnormal.
  73. * WDZST bit is write-once only bit. Align this bit in kernel,
  74. * otherwise kernel code will have no chance to set this bit.
  75. */
  76. setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
  77. }
  78. static struct mm_region imx8m_mem_map[] = {
  79. {
  80. /* ROM */
  81. .virt = 0x0UL,
  82. .phys = 0x0UL,
  83. .size = 0x100000UL,
  84. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  85. PTE_BLOCK_OUTER_SHARE
  86. }, {
  87. /* CAAM */
  88. .virt = 0x100000UL,
  89. .phys = 0x100000UL,
  90. .size = 0x8000UL,
  91. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  92. PTE_BLOCK_NON_SHARE |
  93. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  94. }, {
  95. /* TCM */
  96. .virt = 0x7C0000UL,
  97. .phys = 0x7C0000UL,
  98. .size = 0x80000UL,
  99. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  100. PTE_BLOCK_NON_SHARE |
  101. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  102. }, {
  103. /* OCRAM */
  104. .virt = 0x900000UL,
  105. .phys = 0x900000UL,
  106. .size = 0x200000UL,
  107. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  108. PTE_BLOCK_OUTER_SHARE
  109. }, {
  110. /* AIPS */
  111. .virt = 0xB00000UL,
  112. .phys = 0xB00000UL,
  113. .size = 0x3f500000UL,
  114. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  115. PTE_BLOCK_NON_SHARE |
  116. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  117. }, {
  118. /* DRAM1 */
  119. .virt = 0x40000000UL,
  120. .phys = 0x40000000UL,
  121. .size = PHYS_SDRAM_SIZE,
  122. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  123. PTE_BLOCK_OUTER_SHARE
  124. #ifdef PHYS_SDRAM_2_SIZE
  125. }, {
  126. /* DRAM2 */
  127. .virt = 0x100000000UL,
  128. .phys = 0x100000000UL,
  129. .size = PHYS_SDRAM_2_SIZE,
  130. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  131. PTE_BLOCK_OUTER_SHARE
  132. #endif
  133. }, {
  134. /* empty entrie to split table entry 5 if needed when TEEs are used */
  135. 0,
  136. }, {
  137. /* List terminator */
  138. 0,
  139. }
  140. };
  141. struct mm_region *mem_map = imx8m_mem_map;
  142. void enable_caches(void)
  143. {
  144. /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */
  145. if (rom_pointer[1]) {
  146. /*
  147. * TEE are loaded, So the ddr bank structures
  148. * have been modified update mmu table accordingly
  149. */
  150. int i = 0;
  151. /*
  152. * please make sure that entry initial value matches
  153. * imx8m_mem_map for DRAM1
  154. */
  155. int entry = 5;
  156. u64 attrs = imx8m_mem_map[entry].attrs;
  157. while (i < CONFIG_NR_DRAM_BANKS && entry < 8) {
  158. if (gd->bd->bi_dram[i].start == 0)
  159. break;
  160. imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
  161. imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
  162. imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
  163. imx8m_mem_map[entry].attrs = attrs;
  164. debug("Added memory mapping (%d): %llx %llx\n", entry,
  165. imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
  166. i++; entry++;
  167. }
  168. }
  169. icache_enable();
  170. dcache_enable();
  171. }
  172. __weak int board_phys_sdram_size(phys_size_t *size)
  173. {
  174. if (!size)
  175. return -EINVAL;
  176. *size = PHYS_SDRAM_SIZE;
  177. return 0;
  178. }
  179. int dram_init(void)
  180. {
  181. phys_size_t sdram_size;
  182. int ret;
  183. ret = board_phys_sdram_size(&sdram_size);
  184. if (ret)
  185. return ret;
  186. /* rom_pointer[1] contains the size of TEE occupies */
  187. if (rom_pointer[1])
  188. gd->ram_size = sdram_size - rom_pointer[1];
  189. else
  190. gd->ram_size = sdram_size;
  191. #ifdef PHYS_SDRAM_2_SIZE
  192. gd->ram_size += PHYS_SDRAM_2_SIZE;
  193. #endif
  194. return 0;
  195. }
  196. int dram_init_banksize(void)
  197. {
  198. int bank = 0;
  199. int ret;
  200. phys_size_t sdram_size;
  201. ret = board_phys_sdram_size(&sdram_size);
  202. if (ret)
  203. return ret;
  204. gd->bd->bi_dram[bank].start = PHYS_SDRAM;
  205. if (rom_pointer[1]) {
  206. phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
  207. phys_size_t optee_size = (size_t)rom_pointer[1];
  208. gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
  209. if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) {
  210. if (++bank >= CONFIG_NR_DRAM_BANKS) {
  211. puts("CONFIG_NR_DRAM_BANKS is not enough\n");
  212. return -1;
  213. }
  214. gd->bd->bi_dram[bank].start = optee_start + optee_size;
  215. gd->bd->bi_dram[bank].size = PHYS_SDRAM +
  216. sdram_size - gd->bd->bi_dram[bank].start;
  217. }
  218. } else {
  219. gd->bd->bi_dram[bank].size = sdram_size;
  220. }
  221. #ifdef PHYS_SDRAM_2_SIZE
  222. if (++bank >= CONFIG_NR_DRAM_BANKS) {
  223. puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
  224. return -1;
  225. }
  226. gd->bd->bi_dram[bank].start = PHYS_SDRAM_2;
  227. gd->bd->bi_dram[bank].size = PHYS_SDRAM_2_SIZE;
  228. #endif
  229. return 0;
  230. }
  231. phys_size_t get_effective_memsize(void)
  232. {
  233. /* return the first bank as effective memory */
  234. if (rom_pointer[1])
  235. return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
  236. #ifdef PHYS_SDRAM_2_SIZE
  237. return gd->ram_size - PHYS_SDRAM_2_SIZE;
  238. #else
  239. return gd->ram_size;
  240. #endif
  241. }
  242. static u32 get_cpu_variant_type(u32 type)
  243. {
  244. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  245. struct fuse_bank *bank = &ocotp->bank[1];
  246. struct fuse_bank1_regs *fuse =
  247. (struct fuse_bank1_regs *)bank->fuse_regs;
  248. u32 value = readl(&fuse->tester4);
  249. if (type == MXC_CPU_IMX8MQ) {
  250. if ((value & 0x3) == 0x2)
  251. return MXC_CPU_IMX8MD;
  252. else if (value & 0x200000)
  253. return MXC_CPU_IMX8MQL;
  254. } else if (type == MXC_CPU_IMX8MM) {
  255. switch (value & 0x3) {
  256. case 2:
  257. if (value & 0x1c0000)
  258. return MXC_CPU_IMX8MMDL;
  259. else
  260. return MXC_CPU_IMX8MMD;
  261. case 3:
  262. if (value & 0x1c0000)
  263. return MXC_CPU_IMX8MMSL;
  264. else
  265. return MXC_CPU_IMX8MMS;
  266. default:
  267. if (value & 0x1c0000)
  268. return MXC_CPU_IMX8MML;
  269. break;
  270. }
  271. } else if (type == MXC_CPU_IMX8MN) {
  272. switch (value & 0x3) {
  273. case 2:
  274. if (value & 0x1000000)
  275. return MXC_CPU_IMX8MNDL;
  276. else
  277. return MXC_CPU_IMX8MND;
  278. case 3:
  279. if (value & 0x1000000)
  280. return MXC_CPU_IMX8MNSL;
  281. else
  282. return MXC_CPU_IMX8MNS;
  283. default:
  284. if (value & 0x1000000)
  285. return MXC_CPU_IMX8MNL;
  286. break;
  287. }
  288. } else if (type == MXC_CPU_IMX8MP) {
  289. u32 value0 = readl(&fuse->tester3);
  290. u32 flag = 0;
  291. if ((value0 & 0xc0000) == 0x80000)
  292. return MXC_CPU_IMX8MPD;
  293. /* vpu disabled */
  294. if ((value0 & 0x43000000) == 0x43000000)
  295. flag = 1;
  296. /* npu disabled*/
  297. if ((value & 0x8) == 0x8)
  298. flag |= (1 << 1);
  299. /* isp disabled */
  300. if ((value & 0x3) == 0x3)
  301. flag |= (1 << 2);
  302. switch (flag) {
  303. case 7:
  304. return MXC_CPU_IMX8MPL;
  305. case 2:
  306. return MXC_CPU_IMX8MP6;
  307. default:
  308. break;
  309. }
  310. }
  311. return type;
  312. }
  313. u32 get_cpu_rev(void)
  314. {
  315. struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
  316. u32 reg = readl(&ana_pll->digprog);
  317. u32 type = (reg >> 16) & 0xff;
  318. u32 major_low = (reg >> 8) & 0xff;
  319. u32 rom_version;
  320. reg &= 0xff;
  321. /* iMX8MP */
  322. if (major_low == 0x43) {
  323. type = get_cpu_variant_type(MXC_CPU_IMX8MP);
  324. } else if (major_low == 0x42) {
  325. /* iMX8MN */
  326. type = get_cpu_variant_type(MXC_CPU_IMX8MN);
  327. } else if (major_low == 0x41) {
  328. type = get_cpu_variant_type(MXC_CPU_IMX8MM);
  329. } else {
  330. if (reg == CHIP_REV_1_0) {
  331. /*
  332. * For B0 chip, the DIGPROG is not updated,
  333. * it is still TO1.0. we have to check ROM
  334. * version or OCOTP_READ_FUSE_DATA.
  335. * 0xff0055aa is magic number for B1.
  336. */
  337. if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
  338. reg = CHIP_REV_2_1;
  339. } else {
  340. rom_version =
  341. readl((void __iomem *)ROM_VERSION_A0);
  342. if (rom_version != CHIP_REV_1_0) {
  343. rom_version = readl((void __iomem *)ROM_VERSION_B0);
  344. rom_version &= 0xff;
  345. if (rom_version == CHIP_REV_2_0)
  346. reg = CHIP_REV_2_0;
  347. }
  348. }
  349. }
  350. type = get_cpu_variant_type(type);
  351. }
  352. return (type << 12) | reg;
  353. }
  354. static void imx_set_wdog_powerdown(bool enable)
  355. {
  356. struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
  357. struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
  358. struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
  359. /* Write to the PDE (Power Down Enable) bit */
  360. writew(enable, &wdog1->wmcr);
  361. writew(enable, &wdog2->wmcr);
  362. writew(enable, &wdog3->wmcr);
  363. }
  364. int arch_cpu_init_dm(void)
  365. {
  366. struct udevice *dev;
  367. int ret;
  368. if (CONFIG_IS_ENABLED(CLK)) {
  369. ret = uclass_get_device_by_name(UCLASS_CLK,
  370. "clock-controller@30380000",
  371. &dev);
  372. if (ret < 0) {
  373. printf("Failed to find clock node. Check device tree\n");
  374. return ret;
  375. }
  376. }
  377. return 0;
  378. }
  379. int arch_cpu_init(void)
  380. {
  381. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  382. /*
  383. * ROM might disable clock for SCTR,
  384. * enable the clock before timer_init.
  385. */
  386. if (IS_ENABLED(CONFIG_SPL_BUILD))
  387. clock_enable(CCGR_SCTR, 1);
  388. /*
  389. * Init timer at very early state, because sscg pll setting
  390. * will use it
  391. */
  392. timer_init();
  393. if (IS_ENABLED(CONFIG_SPL_BUILD)) {
  394. clock_init();
  395. imx_set_wdog_powerdown(false);
  396. if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() ||
  397. is_imx8mmsl() || is_imx8mnd() || is_imx8mndl() || is_imx8mns() ||
  398. is_imx8mnsl() || is_imx8mpd()) {
  399. /* Power down cpu core 1, 2 and 3 for iMX8M Dual core or Single core */
  400. struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840);
  401. struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880);
  402. struct pgc_reg *pgc_core3 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x8C0);
  403. struct gpc_reg *gpc = (struct gpc_reg *)GPC_BASE_ADDR;
  404. writel(0x1, &pgc_core2->pgcr);
  405. writel(0x1, &pgc_core3->pgcr);
  406. if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl()) {
  407. writel(0x1, &pgc_core1->pgcr);
  408. writel(0xE, &gpc->cpu_pgc_dn_trg);
  409. } else {
  410. writel(0xC, &gpc->cpu_pgc_dn_trg);
  411. }
  412. }
  413. }
  414. if (is_imx8mq()) {
  415. clock_enable(CCGR_OCOTP, 1);
  416. if (readl(&ocotp->ctrl) & 0x200)
  417. writel(0x200, &ocotp->ctrl_clr);
  418. }
  419. return 0;
  420. }
  421. #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
  422. struct rom_api *g_rom_api = (struct rom_api *)0x980;
  423. enum boot_device get_boot_device(void)
  424. {
  425. volatile gd_t *pgd = gd;
  426. int ret;
  427. u32 boot;
  428. u16 boot_type;
  429. u8 boot_instance;
  430. enum boot_device boot_dev = SD1_BOOT;
  431. ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
  432. ((uintptr_t)&boot) ^ QUERY_BT_DEV);
  433. gd = pgd;
  434. if (ret != ROM_API_OKAY) {
  435. puts("ROMAPI: failure at query_boot_info\n");
  436. return -1;
  437. }
  438. boot_type = boot >> 16;
  439. boot_instance = (boot >> 8) & 0xff;
  440. switch (boot_type) {
  441. case BT_DEV_TYPE_SD:
  442. boot_dev = boot_instance + SD1_BOOT;
  443. break;
  444. case BT_DEV_TYPE_MMC:
  445. boot_dev = boot_instance + MMC1_BOOT;
  446. break;
  447. case BT_DEV_TYPE_NAND:
  448. boot_dev = NAND_BOOT;
  449. break;
  450. case BT_DEV_TYPE_FLEXSPINOR:
  451. boot_dev = QSPI_BOOT;
  452. break;
  453. case BT_DEV_TYPE_USB:
  454. boot_dev = USB_BOOT;
  455. break;
  456. default:
  457. break;
  458. }
  459. return boot_dev;
  460. }
  461. #endif
  462. bool is_usb_boot(void)
  463. {
  464. return get_boot_device() == USB_BOOT;
  465. }
  466. #ifdef CONFIG_OF_SYSTEM_SETUP
  467. bool check_fdt_new_path(void *blob)
  468. {
  469. const char *soc_path = "/soc@0";
  470. int nodeoff;
  471. nodeoff = fdt_path_offset(blob, soc_path);
  472. if (nodeoff < 0)
  473. return false;
  474. return true;
  475. }
  476. static int disable_fdt_nodes(void *blob, const char *const nodes_path[], int size_array)
  477. {
  478. int i = 0;
  479. int rc;
  480. int nodeoff;
  481. const char *status = "disabled";
  482. for (i = 0; i < size_array; i++) {
  483. nodeoff = fdt_path_offset(blob, nodes_path[i]);
  484. if (nodeoff < 0)
  485. continue; /* Not found, skip it */
  486. printf("Found %s node\n", nodes_path[i]);
  487. add_status:
  488. rc = fdt_setprop(blob, nodeoff, "status", status, strlen(status) + 1);
  489. if (rc) {
  490. if (rc == -FDT_ERR_NOSPACE) {
  491. rc = fdt_increase_size(blob, 512);
  492. if (!rc)
  493. goto add_status;
  494. }
  495. printf("Unable to update property %s:%s, err=%s\n",
  496. nodes_path[i], "status", fdt_strerror(rc));
  497. } else {
  498. printf("Modify %s:%s disabled\n",
  499. nodes_path[i], "status");
  500. }
  501. }
  502. return 0;
  503. }
  504. #ifdef CONFIG_IMX8MQ
  505. bool check_dcss_fused(void)
  506. {
  507. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  508. struct fuse_bank *bank = &ocotp->bank[1];
  509. struct fuse_bank1_regs *fuse =
  510. (struct fuse_bank1_regs *)bank->fuse_regs;
  511. u32 value = readl(&fuse->tester4);
  512. if (value & 0x4000000)
  513. return true;
  514. return false;
  515. }
  516. static int disable_mipi_dsi_nodes(void *blob)
  517. {
  518. static const char * const nodes_path[] = {
  519. "/mipi_dsi@30A00000",
  520. "/mipi_dsi_bridge@30A00000",
  521. "/dsi_phy@30A00300",
  522. "/soc@0/bus@30800000/mipi_dsi@30a00000",
  523. "/soc@0/bus@30800000/dphy@30a00300"
  524. };
  525. return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
  526. }
  527. static int disable_dcss_nodes(void *blob)
  528. {
  529. static const char * const nodes_path[] = {
  530. "/dcss@0x32e00000",
  531. "/dcss@32e00000",
  532. "/hdmi@32c00000",
  533. "/hdmi_cec@32c33800",
  534. "/hdmi_drm@32c00000",
  535. "/display-subsystem",
  536. "/sound-hdmi",
  537. "/sound-hdmi-arc",
  538. "/soc@0/bus@32c00000/display-controller@32e00000",
  539. "/soc@0/bus@32c00000/hdmi@32c00000",
  540. };
  541. return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
  542. }
  543. static int check_mipi_dsi_nodes(void *blob)
  544. {
  545. static const char * const lcdif_path[] = {
  546. "/lcdif@30320000",
  547. "/soc@0/bus@30000000/lcdif@30320000"
  548. };
  549. static const char * const mipi_dsi_path[] = {
  550. "/mipi_dsi@30A00000",
  551. "/soc@0/bus@30800000/mipi_dsi@30a00000"
  552. };
  553. static const char * const lcdif_ep_path[] = {
  554. "/lcdif@30320000/port@0/mipi-dsi-endpoint",
  555. "/soc@0/bus@30000000/lcdif@30320000/port@0/endpoint"
  556. };
  557. static const char * const mipi_dsi_ep_path[] = {
  558. "/mipi_dsi@30A00000/port@1/endpoint",
  559. "/soc@0/bus@30800000/mipi_dsi@30a00000/ports/port@0/endpoint"
  560. };
  561. int lookup_node;
  562. int nodeoff;
  563. bool new_path = check_fdt_new_path(blob);
  564. int i = new_path ? 1 : 0;
  565. nodeoff = fdt_path_offset(blob, lcdif_path[i]);
  566. if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff)) {
  567. /*
  568. * If can't find lcdif node or lcdif node is disabled,
  569. * then disable all mipi dsi, since they only can input
  570. * from DCSS
  571. */
  572. return disable_mipi_dsi_nodes(blob);
  573. }
  574. nodeoff = fdt_path_offset(blob, mipi_dsi_path[i]);
  575. if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff))
  576. return 0;
  577. nodeoff = fdt_path_offset(blob, lcdif_ep_path[i]);
  578. if (nodeoff < 0) {
  579. /*
  580. * If can't find lcdif endpoint, then disable all mipi dsi,
  581. * since they only can input from DCSS
  582. */
  583. return disable_mipi_dsi_nodes(blob);
  584. }
  585. lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint");
  586. nodeoff = fdt_path_offset(blob, mipi_dsi_ep_path[i]);
  587. if (nodeoff > 0 && nodeoff == lookup_node)
  588. return 0;
  589. return disable_mipi_dsi_nodes(blob);
  590. }
  591. #endif
  592. int disable_vpu_nodes(void *blob)
  593. {
  594. static const char * const nodes_path_8mq[] = {
  595. "/vpu@38300000",
  596. "/soc@0/vpu@38300000"
  597. };
  598. static const char * const nodes_path_8mm[] = {
  599. "/vpu_g1@38300000",
  600. "/vpu_g2@38310000",
  601. "/vpu_h1@38320000"
  602. };
  603. static const char * const nodes_path_8mp[] = {
  604. "/vpu_g1@38300000",
  605. "/vpu_g2@38310000",
  606. "/vpu_vc8000e@38320000"
  607. };
  608. if (is_imx8mq())
  609. return disable_fdt_nodes(blob, nodes_path_8mq, ARRAY_SIZE(nodes_path_8mq));
  610. else if (is_imx8mm())
  611. return disable_fdt_nodes(blob, nodes_path_8mm, ARRAY_SIZE(nodes_path_8mm));
  612. else if (is_imx8mp())
  613. return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
  614. else
  615. return -EPERM;
  616. }
  617. int disable_gpu_nodes(void *blob)
  618. {
  619. static const char * const nodes_path_8mn[] = {
  620. "/gpu@38000000"
  621. };
  622. return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn));
  623. }
  624. int disable_npu_nodes(void *blob)
  625. {
  626. static const char * const nodes_path_8mp[] = {
  627. "/vipsi@38500000"
  628. };
  629. return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
  630. }
  631. int disable_isp_nodes(void *blob)
  632. {
  633. static const char * const nodes_path_8mp[] = {
  634. "/soc@0/bus@32c00000/camera/isp@32e10000",
  635. "/soc@0/bus@32c00000/camera/isp@32e20000"
  636. };
  637. return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
  638. }
  639. int disable_dsp_nodes(void *blob)
  640. {
  641. static const char * const nodes_path_8mp[] = {
  642. "/dsp@3b6e8000"
  643. };
  644. return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
  645. }
  646. static int disable_cpu_nodes(void *blob, u32 disabled_cores)
  647. {
  648. static const char * const nodes_path[] = {
  649. "/cpus/cpu@1",
  650. "/cpus/cpu@2",
  651. "/cpus/cpu@3",
  652. };
  653. u32 i = 0;
  654. int rc;
  655. int nodeoff;
  656. if (disabled_cores > 3)
  657. return -EINVAL;
  658. i = 3 - disabled_cores;
  659. for (; i < 3; i++) {
  660. nodeoff = fdt_path_offset(blob, nodes_path[i]);
  661. if (nodeoff < 0)
  662. continue; /* Not found, skip it */
  663. debug("Found %s node\n", nodes_path[i]);
  664. rc = fdt_del_node(blob, nodeoff);
  665. if (rc < 0) {
  666. printf("Unable to delete node %s, err=%s\n",
  667. nodes_path[i], fdt_strerror(rc));
  668. } else {
  669. printf("Delete node %s\n", nodes_path[i]);
  670. }
  671. }
  672. return 0;
  673. }
  674. int ft_system_setup(void *blob, struct bd_info *bd)
  675. {
  676. #ifdef CONFIG_IMX8MQ
  677. int i = 0;
  678. int rc;
  679. int nodeoff;
  680. if (get_boot_device() == USB_BOOT) {
  681. disable_dcss_nodes(blob);
  682. bool new_path = check_fdt_new_path(blob);
  683. int v = new_path ? 1 : 0;
  684. static const char * const usb_dwc3_path[] = {
  685. "/usb@38100000/dwc3",
  686. "/soc@0/usb@38100000"
  687. };
  688. nodeoff = fdt_path_offset(blob, usb_dwc3_path[v]);
  689. if (nodeoff >= 0) {
  690. const char *speed = "high-speed";
  691. printf("Found %s node\n", usb_dwc3_path[v]);
  692. usb_modify_speed:
  693. rc = fdt_setprop(blob, nodeoff, "maximum-speed", speed, strlen(speed) + 1);
  694. if (rc) {
  695. if (rc == -FDT_ERR_NOSPACE) {
  696. rc = fdt_increase_size(blob, 512);
  697. if (!rc)
  698. goto usb_modify_speed;
  699. }
  700. printf("Unable to set property %s:%s, err=%s\n",
  701. usb_dwc3_path[v], "maximum-speed", fdt_strerror(rc));
  702. } else {
  703. printf("Modify %s:%s = %s\n",
  704. usb_dwc3_path[v], "maximum-speed", speed);
  705. }
  706. } else {
  707. printf("Can't found %s node\n", usb_dwc3_path[v]);
  708. }
  709. }
  710. /* Disable the CPU idle for A0 chip since the HW does not support it */
  711. if (is_soc_rev(CHIP_REV_1_0)) {
  712. static const char * const nodes_path[] = {
  713. "/cpus/cpu@0",
  714. "/cpus/cpu@1",
  715. "/cpus/cpu@2",
  716. "/cpus/cpu@3",
  717. };
  718. for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
  719. nodeoff = fdt_path_offset(blob, nodes_path[i]);
  720. if (nodeoff < 0)
  721. continue; /* Not found, skip it */
  722. debug("Found %s node\n", nodes_path[i]);
  723. rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
  724. if (rc == -FDT_ERR_NOTFOUND)
  725. continue;
  726. if (rc) {
  727. printf("Unable to update property %s:%s, err=%s\n",
  728. nodes_path[i], "status", fdt_strerror(rc));
  729. return rc;
  730. }
  731. debug("Remove %s:%s\n", nodes_path[i],
  732. "cpu-idle-states");
  733. }
  734. }
  735. if (is_imx8mql()) {
  736. disable_vpu_nodes(blob);
  737. if (check_dcss_fused()) {
  738. printf("DCSS is fused\n");
  739. disable_dcss_nodes(blob);
  740. check_mipi_dsi_nodes(blob);
  741. }
  742. }
  743. if (is_imx8md())
  744. disable_cpu_nodes(blob, 2);
  745. #elif defined(CONFIG_IMX8MM)
  746. if (is_imx8mml() || is_imx8mmdl() || is_imx8mmsl())
  747. disable_vpu_nodes(blob);
  748. if (is_imx8mmd() || is_imx8mmdl())
  749. disable_cpu_nodes(blob, 2);
  750. else if (is_imx8mms() || is_imx8mmsl())
  751. disable_cpu_nodes(blob, 3);
  752. #elif defined(CONFIG_IMX8MN)
  753. if (is_imx8mnl() || is_imx8mndl() || is_imx8mnsl())
  754. disable_gpu_nodes(blob);
  755. if (is_imx8mnd() || is_imx8mndl())
  756. disable_cpu_nodes(blob, 2);
  757. else if (is_imx8mns() || is_imx8mnsl())
  758. disable_cpu_nodes(blob, 3);
  759. #elif defined(CONFIG_IMX8MP)
  760. if (is_imx8mpl())
  761. disable_vpu_nodes(blob);
  762. if (is_imx8mpl() || is_imx8mp6())
  763. disable_npu_nodes(blob);
  764. if (is_imx8mpl())
  765. disable_isp_nodes(blob);
  766. if (is_imx8mpl() || is_imx8mp6())
  767. disable_dsp_nodes(blob);
  768. if (is_imx8mpd())
  769. disable_cpu_nodes(blob, 2);
  770. #endif
  771. return 0;
  772. }
  773. #endif
  774. #if !CONFIG_IS_ENABLED(SYSRESET)
  775. void reset_cpu(ulong addr)
  776. {
  777. struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
  778. /* Clear WDA to trigger WDOG_B immediately */
  779. writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr);
  780. while (1) {
  781. /*
  782. * spin for .5 seconds before reset
  783. */
  784. }
  785. }
  786. #endif
  787. #if defined(CONFIG_ARCH_MISC_INIT)
  788. static void acquire_buildinfo(void)
  789. {
  790. u64 atf_commit = 0;
  791. struct arm_smccc_res res;
  792. /* Get ARM Trusted Firmware commit id */
  793. arm_smccc_smc(IMX_SIP_BUILDINFO, IMX_SIP_BUILDINFO_GET_COMMITHASH,
  794. 0, 0, 0, 0, 0, 0, &res);
  795. atf_commit = res.a0;
  796. if (atf_commit == 0xffffffff) {
  797. debug("ATF does not support build info\n");
  798. atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */
  799. }
  800. printf("\n BuildInfo:\n - ATF %s\n\n", (char *)&atf_commit);
  801. }
  802. int arch_misc_init(void)
  803. {
  804. acquire_buildinfo();
  805. return 0;
  806. }
  807. #endif
  808. void imx_tmu_arch_init(void *reg_base)
  809. {
  810. if (is_imx8mm() || is_imx8mn()) {
  811. /* Load TCALIV and TASR from fuses */
  812. struct ocotp_regs *ocotp =
  813. (struct ocotp_regs *)OCOTP_BASE_ADDR;
  814. struct fuse_bank *bank = &ocotp->bank[3];
  815. struct fuse_bank3_regs *fuse =
  816. (struct fuse_bank3_regs *)bank->fuse_regs;
  817. u32 tca_rt, tca_hr, tca_en;
  818. u32 buf_vref, buf_slope;
  819. tca_rt = fuse->ana0 & 0xFF;
  820. tca_hr = (fuse->ana0 & 0xFF00) >> 8;
  821. tca_en = (fuse->ana0 & 0x2000000) >> 25;
  822. buf_vref = (fuse->ana0 & 0x1F00000) >> 20;
  823. buf_slope = (fuse->ana0 & 0xF0000) >> 16;
  824. writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
  825. writel((tca_en << 31) | (tca_hr << 16) | tca_rt,
  826. (ulong)reg_base + 0x30);
  827. }
  828. #ifdef CONFIG_IMX8MP
  829. /* Load TCALIV0/1/m40 and TRIM from fuses */
  830. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  831. struct fuse_bank *bank = &ocotp->bank[38];
  832. struct fuse_bank38_regs *fuse =
  833. (struct fuse_bank38_regs *)bank->fuse_regs;
  834. struct fuse_bank *bank2 = &ocotp->bank[39];
  835. struct fuse_bank39_regs *fuse2 =
  836. (struct fuse_bank39_regs *)bank2->fuse_regs;
  837. u32 buf_vref, buf_slope, bjt_cur, vlsb, bgr;
  838. u32 reg;
  839. u32 tca40[2], tca25[2], tca105[2];
  840. /* For blank sample */
  841. if (!fuse->ana_trim2 && !fuse->ana_trim3 &&
  842. !fuse->ana_trim4 && !fuse2->ana_trim5) {
  843. /* Use a default 25C binary codes */
  844. tca25[0] = 1596;
  845. tca25[1] = 1596;
  846. writel(tca25[0], (ulong)reg_base + 0x30);
  847. writel(tca25[1], (ulong)reg_base + 0x34);
  848. return;
  849. }
  850. buf_vref = (fuse->ana_trim2 & 0xc0) >> 6;
  851. buf_slope = (fuse->ana_trim2 & 0xF00) >> 8;
  852. bjt_cur = (fuse->ana_trim2 & 0xF000) >> 12;
  853. bgr = (fuse->ana_trim2 & 0xF0000) >> 16;
  854. vlsb = (fuse->ana_trim2 & 0xF00000) >> 20;
  855. writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
  856. reg = (bgr << 28) | (bjt_cur << 20) | (vlsb << 12) | (1 << 7);
  857. writel(reg, (ulong)reg_base + 0x3c);
  858. tca40[0] = (fuse->ana_trim3 & 0xFFF0000) >> 16;
  859. tca25[0] = (fuse->ana_trim3 & 0xF0000000) >> 28;
  860. tca25[0] |= ((fuse->ana_trim4 & 0xFF) << 4);
  861. tca105[0] = (fuse->ana_trim4 & 0xFFF00) >> 8;
  862. tca40[1] = (fuse->ana_trim4 & 0xFFF00000) >> 20;
  863. tca25[1] = fuse2->ana_trim5 & 0xFFF;
  864. tca105[1] = (fuse2->ana_trim5 & 0xFFF000) >> 12;
  865. /* use 25c for 1p calibration */
  866. writel(tca25[0] | (tca105[0] << 16), (ulong)reg_base + 0x30);
  867. writel(tca25[1] | (tca105[1] << 16), (ulong)reg_base + 0x34);
  868. writel(tca40[0] | (tca40[1] << 16), (ulong)reg_base + 0x38);
  869. #endif
  870. }
  871. #if defined(CONFIG_SPL_BUILD)
  872. #if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
  873. bool serror_need_skip = true;
  874. void do_error(struct pt_regs *pt_regs, unsigned int esr)
  875. {
  876. /*
  877. * If stack is still in ROM reserved OCRAM not switch to SPL,
  878. * it is the ROM SError
  879. */
  880. ulong sp;
  881. asm volatile("mov %0, sp" : "=r"(sp) : );
  882. if (serror_need_skip && sp < 0x910000 && sp >= 0x900000) {
  883. /* Check for ERR050342, imx8mq HDCP enabled parts */
  884. if (is_imx8mq() && !(readl(OCOTP_BASE_ADDR + 0x450) & 0x08000000)) {
  885. serror_need_skip = false;
  886. return; /* Do nothing skip the SError in ROM */
  887. }
  888. /* Check for ERR050350, field return mode for imx8mq, mm and mn */
  889. if (readl(OCOTP_BASE_ADDR + 0x630) & 0x1) {
  890. serror_need_skip = false;
  891. return; /* Do nothing skip the SError in ROM */
  892. }
  893. }
  894. efi_restore_gd();
  895. printf("\"Error\" handler, esr 0x%08x\n", esr);
  896. show_regs(pt_regs);
  897. panic("Resetting CPU ...\n");
  898. }
  899. #endif
  900. #endif
  901. #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
  902. enum env_location env_get_location(enum env_operation op, int prio)
  903. {
  904. enum boot_device dev = get_boot_device();
  905. enum env_location env_loc = ENVL_UNKNOWN;
  906. if (prio)
  907. return env_loc;
  908. switch (dev) {
  909. #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
  910. case QSPI_BOOT:
  911. env_loc = ENVL_SPI_FLASH;
  912. break;
  913. #endif
  914. #ifdef CONFIG_ENV_IS_IN_NAND
  915. case NAND_BOOT:
  916. env_loc = ENVL_NAND;
  917. break;
  918. #endif
  919. #ifdef CONFIG_ENV_IS_IN_MMC
  920. case SD1_BOOT:
  921. case SD2_BOOT:
  922. case SD3_BOOT:
  923. case MMC1_BOOT:
  924. case MMC2_BOOT:
  925. case MMC3_BOOT:
  926. env_loc = ENVL_MMC;
  927. break;
  928. #endif
  929. default:
  930. #if defined(CONFIG_ENV_IS_NOWHERE)
  931. env_loc = ENVL_NOWHERE;
  932. #endif
  933. break;
  934. }
  935. return env_loc;
  936. }
  937. #ifndef ENV_IS_EMBEDDED
  938. long long env_get_offset(long long defautl_offset)
  939. {
  940. enum boot_device dev = get_boot_device();
  941. switch (dev) {
  942. case NAND_BOOT:
  943. return (60 << 20); /* 60MB offset for NAND */
  944. default:
  945. break;
  946. }
  947. return defautl_offset;
  948. }
  949. #endif
  950. #endif