ids8313.h 14 KB

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  1. /*
  2. * (C) Copyright 2013
  3. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  4. *
  5. * Based on:
  6. * Copyright (c) 2011 IDS GmbH, Germany
  7. * Sergej Stepanov <ste@ids.de>
  8. *
  9. * SPDX-License-Identifier: GPL-2.0+
  10. */
  11. #ifndef __CONFIG_H
  12. #define __CONFIG_H
  13. /*
  14. * High Level Configuration Options
  15. */
  16. #define CONFIG_MPC831x
  17. #define CONFIG_MPC8313
  18. #define CONFIG_FSL_ELBC
  19. #define CONFIG_MISC_INIT_R
  20. #define CONFIG_BOOT_RETRY_TIME 900
  21. #define CONFIG_BOOT_RETRY_MIN 30
  22. #define CONFIG_RESET_TO_RETRY
  23. #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
  24. #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
  25. #define CONFIG_SYS_IMMR 0xF0000000
  26. #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
  27. #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
  28. /*
  29. * Hardware Reset Configuration Word
  30. * if CLKIN is 66.000MHz, then
  31. * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz
  32. */
  33. #define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\
  34. HRCWL_DDR_TO_SCB_CLK_2X1 |\
  35. HRCWL_CSB_TO_CLKIN_2X1 |\
  36. HRCWL_CORE_TO_CSB_2X1)
  37. #define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST |\
  38. HRCWH_CORE_ENABLE |\
  39. HRCWH_FROM_0XFFF00100 |\
  40. HRCWH_BOOTSEQ_DISABLE |\
  41. HRCWH_SW_WATCHDOG_DISABLE |\
  42. HRCWH_ROM_LOC_LOCAL_8BIT |\
  43. HRCWH_RL_EXT_LEGACY |\
  44. HRCWH_TSEC1M_IN_MII |\
  45. HRCWH_TSEC2M_IN_MII |\
  46. HRCWH_BIG_ENDIAN)
  47. #define CONFIG_SYS_SICRH 0x00000000
  48. #define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
  49. #define CONFIG_HWCONFIG
  50. #define CONFIG_SYS_HID0_INIT 0x000000000
  51. #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK |\
  52. HID0_ENABLE_INSTRUCTION_CACHE |\
  53. HID0_DISABLE_DYNAMIC_POWER_MANAGMENT)
  54. #define CONFIG_SYS_HID2 (HID2_HBE | 0x00020000)
  55. /*
  56. * Definitions for initial stack pointer and data area (in DCACHE )
  57. */
  58. #define CONFIG_SYS_INIT_RAM_LOCK
  59. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
  60. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */
  61. #define CONFIG_SYS_GBL_DATA_SIZE 0x100
  62. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
  63. - CONFIG_SYS_GBL_DATA_SIZE)
  64. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  65. /*
  66. * Local Bus LCRR and LBCR regs
  67. */
  68. #define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
  69. #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
  70. #define CONFIG_SYS_LBC_LBCR (0x00040000 |\
  71. (0xFF << LBCR_BMT_SHIFT) |\
  72. 0xF)
  73. #define CONFIG_SYS_LBC_MRTPR 0x20000000
  74. /*
  75. * Internal Definitions
  76. */
  77. /*
  78. * DDR Setup
  79. */
  80. #define CONFIG_SYS_DDR_BASE 0x00000000
  81. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  82. #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
  83. /*
  84. * Manually set up DDR parameters,
  85. * as this board has not the SPD connected to I2C.
  86. */
  87. #define CONFIG_SYS_DDR_SIZE 256 /* MB */
  88. #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\
  89. 0x00010000 |\
  90. CSCONFIG_ROW_BIT_13 |\
  91. CSCONFIG_COL_BIT_10)
  92. #define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \
  93. CSCONFIG_BANK_BIT_3)
  94. #define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */
  95. #define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\
  96. (3 << TIMING_CFG0_WRT_SHIFT) |\
  97. (3 << TIMING_CFG0_RRT_SHIFT) |\
  98. (3 << TIMING_CFG0_WWT_SHIFT) |\
  99. (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
  100. (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
  101. (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
  102. (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  103. #define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
  104. (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
  105. (4 << TIMING_CFG1_ACTTORW_SHIFT) |\
  106. (7 << TIMING_CFG1_CASLAT_SHIFT) |\
  107. (4 << TIMING_CFG1_REFREC_SHIFT) |\
  108. (4 << TIMING_CFG1_WRREC_SHIFT) |\
  109. (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
  110. (2 << TIMING_CFG1_WRTORD_SHIFT))
  111. #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
  112. (5 << TIMING_CFG2_CPO_SHIFT) |\
  113. (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
  114. (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
  115. (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
  116. (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
  117. (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
  118. #define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
  119. (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  120. #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\
  121. SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
  122. SDRAM_CFG_DBW_32 |\
  123. SDRAM_CFG_SDRAM_TYPE_DDR2)
  124. #define CONFIG_SYS_SDRAM_CFG2 0x00401000
  125. #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
  126. (0x0242 << SDRAM_MODE_SD_SHIFT))
  127. #define CONFIG_SYS_DDR_MODE_2 0x00000000
  128. #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
  129. #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\
  130. DDRCDR_PZ_NOMZ |\
  131. DDRCDR_NZ_NOMZ |\
  132. DDRCDR_ODT |\
  133. DDRCDR_M_ODR |\
  134. DDRCDR_Q_DRN)
  135. /*
  136. * on-board devices
  137. */
  138. #define CONFIG_TSEC1
  139. #define CONFIG_TSEC2
  140. #define CONFIG_HARD_SPI
  141. /*
  142. * NOR FLASH setup
  143. */
  144. #define CONFIG_SYS_FLASH_CFI
  145. #define CONFIG_FLASH_CFI_DRIVER
  146. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
  147. #define CONFIG_FLASH_SHOW_PROGRESS 50
  148. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  149. #define CONFIG_SYS_FLASH_BASE 0xFF800000
  150. #define CONFIG_SYS_FLASH_SIZE 8
  151. #define CONFIG_SYS_FLASH_PROTECTION
  152. #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
  153. #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016
  154. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
  155. BR_PS_8 |\
  156. BR_MS_GPCM |\
  157. BR_V)
  158. #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
  159. OR_GPCM_SCY_10 |\
  160. OR_GPCM_EHTR |\
  161. OR_GPCM_TRLX |\
  162. OR_GPCM_CSNT |\
  163. OR_GPCM_EAD)
  164. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  165. #define CONFIG_SYS_MAX_FLASH_SECT 128
  166. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000
  167. #define CONFIG_SYS_FLASH_WRITE_TOUT 500
  168. /*
  169. * NAND FLASH setup
  170. */
  171. #define CONFIG_SYS_NAND_BASE 0xE1000000
  172. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  173. #define CONFIG_SYS_NAND_MAX_CHIPS 1
  174. #define CONFIG_NAND_FSL_ELBC
  175. #define CONFIG_SYS_NAND_PAGE_SIZE (2048)
  176. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
  177. #define NAND_CACHE_PAGES 64
  178. #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
  179. #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E
  180. #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
  181. #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
  182. #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE) |\
  183. (2<<BR_DECC_SHIFT) |\
  184. BR_PS_8 |\
  185. BR_MS_FCM |\
  186. BR_V)
  187. #define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 |\
  188. OR_FCM_PGS |\
  189. OR_FCM_CSCT |\
  190. OR_FCM_CST |\
  191. OR_FCM_CHT |\
  192. OR_FCM_SCY_4 |\
  193. OR_FCM_TRLX |\
  194. OR_FCM_EHTR |\
  195. OR_FCM_RST)
  196. /*
  197. * MRAM setup
  198. */
  199. #define CONFIG_SYS_MRAM_BASE 0xE2000000
  200. #define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */
  201. #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_MRAM_BASE
  202. #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* 128 Kb */
  203. #define CONFIG_SYS_OR_TIMING_MRAM
  204. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_MRAM_BASE |\
  205. BR_PS_8 |\
  206. BR_MS_GPCM |\
  207. BR_V)
  208. #define CONFIG_SYS_OR2_PRELIM 0xFFFE0C74
  209. /*
  210. * CPLD setup
  211. */
  212. #define CONFIG_SYS_CPLD_BASE 0xE3000000
  213. #define CONFIG_SYS_CPLD_SIZE 0x8000
  214. #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CPLD_BASE
  215. #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E
  216. #define CONFIG_SYS_OR_TIMING_MRAM
  217. #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CPLD_BASE |\
  218. BR_PS_8 |\
  219. BR_MS_GPCM |\
  220. BR_V)
  221. #define CONFIG_SYS_OR3_PRELIM 0xFFFF8814
  222. /*
  223. * HW-Watchdog
  224. */
  225. #define CONFIG_WATCHDOG 1
  226. #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
  227. /*
  228. * I2C setup
  229. */
  230. #define CONFIG_SYS_I2C
  231. #define CONFIG_SYS_I2C_FSL
  232. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  233. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  234. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
  235. #define CONFIG_RTC_PCF8563
  236. #define CONFIG_SYS_I2C_RTC_ADDR 0x51
  237. /*
  238. * SPI setup
  239. */
  240. #ifdef CONFIG_HARD_SPI
  241. #define CONFIG_SYS_GPIO1_PRELIM
  242. #define CONFIG_SYS_GPIO1_DIR 0x00000001
  243. #define CONFIG_SYS_GPIO1_DAT 0x00000001
  244. #endif
  245. /*
  246. * Ethernet setup
  247. */
  248. #ifdef CONFIG_TSEC1
  249. #define CONFIG_HAS_ETH0
  250. #define CONFIG_TSEC1_NAME "TSEC0"
  251. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  252. #define TSEC1_PHY_ADDR 0x1
  253. #define TSEC1_FLAGS TSEC_GIGABIT
  254. #define TSEC1_PHYIDX 0
  255. #endif
  256. #ifdef CONFIG_TSEC2
  257. #define CONFIG_HAS_ETH1
  258. #define CONFIG_TSEC2_NAME "TSEC1"
  259. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  260. #define TSEC2_PHY_ADDR 0x3
  261. #define TSEC2_FLAGS TSEC_GIGABIT
  262. #define TSEC2_PHYIDX 0
  263. #endif
  264. #define CONFIG_ETHPRIME "TSEC1"
  265. /*
  266. * Serial Port
  267. */
  268. #define CONFIG_SYS_NS16550_SERIAL
  269. #define CONFIG_SYS_NS16550_REG_SIZE 1
  270. #define CONFIG_SYS_BAUDRATE_TABLE \
  271. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  272. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
  273. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
  274. #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
  275. #define CONFIG_HAS_FSL_DR_USB
  276. #define CONFIG_SYS_SCCR_USBDRCM 3
  277. /*
  278. * BAT's
  279. */
  280. #define CONFIG_HIGH_BATS
  281. /* DDR @ 0x00000000 */
  282. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE |\
  283. BATL_PP_10)
  284. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE |\
  285. BATU_BL_256M |\
  286. BATU_VS |\
  287. BATU_VP)
  288. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  289. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  290. /* Initial RAM @ 0xFD000000 */
  291. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR |\
  292. BATL_PP_10 |\
  293. BATL_GUARDEDSTORAGE)
  294. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR |\
  295. BATU_BL_256K |\
  296. BATU_VS |\
  297. BATU_VP)
  298. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  299. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  300. /* FLASH @ 0xFF800000 */
  301. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE |\
  302. BATL_PP_10 |\
  303. BATL_GUARDEDSTORAGE)
  304. #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE |\
  305. BATU_BL_8M |\
  306. BATU_VS |\
  307. BATU_VP)
  308. #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE |\
  309. BATL_PP_10 |\
  310. BATL_CACHEINHIBIT |\
  311. BATL_GUARDEDSTORAGE)
  312. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  313. #define CONFIG_SYS_IBAT3L (0)
  314. #define CONFIG_SYS_IBAT3U (0)
  315. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  316. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  317. #define CONFIG_SYS_IBAT4L (0)
  318. #define CONFIG_SYS_IBAT4U (0)
  319. #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
  320. #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
  321. /* IMMRBAR @ 0xF0000000 */
  322. #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR |\
  323. BATL_PP_10 |\
  324. BATL_CACHEINHIBIT |\
  325. BATL_GUARDEDSTORAGE)
  326. #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR |\
  327. BATU_BL_128M |\
  328. BATU_VS |\
  329. BATU_VP)
  330. #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
  331. #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
  332. /* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */
  333. #define CONFIG_SYS_IBAT6L (0xE0000000 |\
  334. BATL_PP_10 |\
  335. BATL_GUARDEDSTORAGE)
  336. #define CONFIG_SYS_IBAT6U (0xE0000000 |\
  337. BATU_BL_256M |\
  338. BATU_VS |\
  339. BATU_VP)
  340. #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
  341. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  342. #define CONFIG_SYS_IBAT7L (0)
  343. #define CONFIG_SYS_IBAT7U (0)
  344. #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
  345. #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  346. /*
  347. * U-Boot environment setup
  348. */
  349. #define CONFIG_BOOTP_BOOTFILESIZE
  350. /*
  351. * The reserved memory
  352. */
  353. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  354. #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  355. #define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024)
  356. /*
  357. * Environment Configuration
  358. */
  359. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
  360. + CONFIG_SYS_MONITOR_LEN)
  361. #define CONFIG_ENV_SIZE 0x20000
  362. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
  363. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  364. #define CONFIG_NETDEV eth1
  365. #define CONFIG_HOSTNAME "ids8313"
  366. #define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx"
  367. #define CONFIG_BOOTFILE "ids8313/uImage"
  368. #define CONFIG_UBOOTPATH "ids8313/u-boot.bin"
  369. #define CONFIG_FDTFILE "ids8313/ids8313.dtb"
  370. #define CONFIG_LOADADDR 0x400000
  371. #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
  372. /* Initial Memory map for Linux*/
  373. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  374. /*
  375. * Miscellaneous configurable options
  376. */
  377. #define CONFIG_SYS_CBSIZE 1024
  378. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  379. #define CONFIG_SYS_MEMTEST_START 0x00001000
  380. #define CONFIG_SYS_MEMTEST_END 0x00C00000
  381. #define CONFIG_SYS_LOAD_ADDR 0x100000
  382. #define CONFIG_MII
  383. #define CONFIG_LOADS_ECHO
  384. #define CONFIG_TIMESTAMP
  385. #define CONFIG_PREBOOT "echo;" \
  386. "echo Type \\\"run nfsboot\\\" " \
  387. "to mount root filesystem over NFS;echo"
  388. #define CONFIG_BOOTCOMMAND "run boot_cramfs"
  389. #undef CONFIG_SYS_LOADS_BAUD_CHANGE
  390. #define CONFIG_JFFS2_NAND
  391. #define CONFIG_JFFS2_DEV "0"
  392. /* mtdparts command line support */
  393. #define CONFIG_FLASH_CFI_MTD
  394. #define CONFIG_MTD_DEVICE
  395. #define CONFIG_EXTRA_ENV_SETTINGS \
  396. "netdev=" __stringify(CONFIG_NETDEV) "\0" \
  397. "ethprime=TSEC1\0" \
  398. "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  399. "tftpflash=tftpboot ${loadaddr} ${uboot}; " \
  400. "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
  401. " +${filesize}; " \
  402. "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
  403. " +${filesize}; " \
  404. "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
  405. " ${filesize}; " \
  406. "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
  407. " +${filesize}; " \
  408. "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \
  409. " ${filesize}\0" \
  410. "console=ttyS0\0" \
  411. "fdtaddr=0x780000\0" \
  412. "kernel_addr=ff800000\0" \
  413. "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \
  414. "setbootargs=setenv bootargs " \
  415. "root=${rootdev} rw console=${console}," \
  416. "${baudrate} ${othbootargs}\0" \
  417. "setipargs=setenv bootargs root=${rootdev} rw " \
  418. "nfsroot=${serverip}:${rootpath} " \
  419. "ip=${ipaddr}:${serverip}:${gatewayip}:" \
  420. "${netmask}:${hostname}:${netdev}:off " \
  421. "console=${console},${baudrate} ${othbootargs}\0" \
  422. "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
  423. "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
  424. "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
  425. "\0"
  426. #define CONFIG_NFSBOOTCOMMAND \
  427. "setenv rootdev /dev/nfs;" \
  428. "run setipargs;run addmtd;" \
  429. "tftp ${loadaddr} ${bootfile};" \
  430. "tftp ${fdtaddr} ${fdtfile};" \
  431. "fdt addr ${fdtaddr};" \
  432. "bootm ${loadaddr} - ${fdtaddr}"
  433. /* UBI Support */
  434. #define CONFIG_MTD_PARTITIONS
  435. #endif /* __CONFIG_H */