// SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2019 NXP */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include DECLARE_GLOBAL_DATA_PTR; int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { case SD2_BOOT: case MMC2_BOOT: return BOOT_DEVICE_MMC1; case SD3_BOOT: case MMC3_BOOT: return BOOT_DEVICE_MMC2; default: return BOOT_DEVICE_NONE; } } static void spl_dram_init(void) { ddr_init(&dram_timing); } void spl_board_init(void) { puts("Normal Boot\n"); } #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { /* Just empty function now - can't decide what to choose */ debug("%s: %s\n", __func__, name); return 0; } #endif #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) static iomux_v3_cfg_t const uart_pads[] = { IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), }; static iomux_v3_cfg_t const wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; int board_early_init_f(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); set_wdog_reset(wdog); imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); return 0; } static int power_init_board(void) { struct udevice *dev; int ret; ret = pmic_get("pmic@4b", &dev); if (ret == -ENODEV) { puts("No pmic\n"); return 0; } if (ret != 0) return ret; /* decrease RESET key long push time from the default 10s to 10ms */ pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0); /* unlock the PMIC regs */ pmic_reg_write(dev, BD718XX_REGLOCK, 0x1); /* increase VDD_SOC to typical value 0.85v before first DRAM access */ pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f); /* increase VDD_DRAM to 0.975v for 3Ghz DDR */ pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83); #ifndef CONFIG_IMX8M_LPDDR4 /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */ pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28); #endif /* lock the PMIC regs */ pmic_reg_write(dev, BD718XX_REGLOCK, 0x11); return 0; } void board_init_f(ulong dummy) { struct udevice *dev; int ret; arch_cpu_init(); init_uart_clk(1); board_early_init_f(); timer_init(); preloader_console_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); hang(); } ret = uclass_get_device_by_name(UCLASS_CLK, "clock-controller@30380000", &dev); if (ret < 0) { printf("Failed to find clock node. Check device tree\n"); hang(); } enable_tzc380(); power_init_board(); /* DDR initialization */ spl_dram_init(); board_init_r(NULL, 0); }