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@@ -0,0 +1,570 @@
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+/*
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+ * Copyright 2016 Timesys Corporation
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+ * Copyright 2016 Advantech Corporation
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+ * Copyright 2012 Freescale Semiconductor, Inc.
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+ *
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+ * SPDX-License-Identifier: GPL-2.0+
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+ */
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+
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+#include <asm/arch/clock.h>
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+#include <asm/arch/imx-regs.h>
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+#include <asm/arch/iomux.h>
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+#include <asm/arch/mx6-pins.h>
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+#include <asm/errno.h>
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+#include <asm/gpio.h>
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+#include <asm/imx-common/mxc_i2c.h>
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+#include <asm/imx-common/iomux-v3.h>
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+#include <asm/imx-common/boot_mode.h>
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+#include <asm/imx-common/video.h>
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+#include <mmc.h>
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+#include <fsl_esdhc.h>
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+#include <miiphy.h>
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+#include <netdev.h>
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+#include <asm/arch/mxc_hdmi.h>
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+#include <asm/arch/crm_regs.h>
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+#include <asm/io.h>
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+#include <asm/arch/sys_proto.h>
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+#include <i2c.h>
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+#include <pwm.h>
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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+ PAD_CTL_HYS)
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+
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+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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+
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+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
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+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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+
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+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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+ PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
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+
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+#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
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+ PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
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+
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+#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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+ PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
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+
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+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
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+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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+
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+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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+
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+#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
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+
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+int dram_init(void)
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+{
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+ gd->ram_size = imx_ddr_size();
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+
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+ return 0;
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+}
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+
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+static iomux_v3_cfg_t const uart3_pads[] = {
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+ MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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+ MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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+ MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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+ MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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+};
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+
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+static iomux_v3_cfg_t const uart4_pads[] = {
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+ MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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+ MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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+};
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+
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+static iomux_v3_cfg_t const enet_pads[] = {
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+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
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+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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+ /* AR8033 PHY Reset */
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+ MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
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+};
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+
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+static void setup_iomux_enet(void)
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+{
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+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
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+
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+ /* Reset AR8033 PHY */
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+ gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
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+ udelay(500);
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+ gpio_set_value(IMX_GPIO_NR(1, 28), 1);
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+}
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+
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+static iomux_v3_cfg_t const usdhc2_pads[] = {
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+ MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
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+};
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+
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+static iomux_v3_cfg_t const usdhc3_pads[] = {
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+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+};
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+
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+static iomux_v3_cfg_t const usdhc4_pads[] = {
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+ MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
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+ MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
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+};
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+
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+static iomux_v3_cfg_t const ecspi1_pads[] = {
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+ MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
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+ MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
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+ MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
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+ MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
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+};
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+
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+static struct i2c_pads_info i2c_pad_info1 = {
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+ .scl = {
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+ .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
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+ .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
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+ .gp = IMX_GPIO_NR(5, 27)
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+ },
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+ .sda = {
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+ .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
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+ .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
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+ .gp = IMX_GPIO_NR(5, 26)
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+ }
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+};
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+
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+static struct i2c_pads_info i2c_pad_info2 = {
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+ .scl = {
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+ .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
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+ .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
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+ .gp = IMX_GPIO_NR(4, 12)
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+ },
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+ .sda = {
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+ .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
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+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
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+ .gp = IMX_GPIO_NR(4, 13)
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+ }
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+};
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+
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+static struct i2c_pads_info i2c_pad_info3 = {
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+ .scl = {
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+ .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
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+ .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
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+ .gp = IMX_GPIO_NR(1, 3)
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+ },
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+ .sda = {
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+ .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
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+ .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
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+ .gp = IMX_GPIO_NR(1, 6)
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+ }
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+};
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+
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+#ifdef CONFIG_MXC_SPI
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+int board_spi_cs_gpio(unsigned bus, unsigned cs)
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+{
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+ return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
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+}
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+
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+static void setup_spi(void)
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+{
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+ imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
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+}
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+#endif
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+
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+static iomux_v3_cfg_t const pcie_pads[] = {
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+ MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
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+ MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
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+};
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+
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+static void setup_pcie(void)
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+{
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+ imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
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+}
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+
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+static void setup_iomux_uart(void)
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+{
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+ imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
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+ imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
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+}
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+
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+#ifdef CONFIG_FSL_ESDHC
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+struct fsl_esdhc_cfg usdhc_cfg[3] = {
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+ {USDHC2_BASE_ADDR},
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+ {USDHC3_BASE_ADDR},
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+ {USDHC4_BASE_ADDR},
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+};
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+
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+#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
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+#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 11)
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+
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+int board_mmc_getcd(struct mmc *mmc)
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+{
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+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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+ int ret = 0;
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+
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+ switch (cfg->esdhc_base) {
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+ case USDHC2_BASE_ADDR:
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+ ret = !gpio_get_value(USDHC2_CD_GPIO);
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+ break;
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+ case USDHC3_BASE_ADDR:
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+ ret = 1; /* eMMC is always present */
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+ break;
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+ case USDHC4_BASE_ADDR:
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+ ret = !gpio_get_value(USDHC4_CD_GPIO);
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+ break;
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+ }
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+
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+ return ret;
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+}
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+
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+int board_mmc_init(bd_t *bis)
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+{
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+ int ret;
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+ int i;
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+
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+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
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+ switch (i) {
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+ case 0:
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+ imx_iomux_v3_setup_multiple_pads(
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+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
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+ gpio_direction_input(USDHC2_CD_GPIO);
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+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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+ break;
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+ case 1:
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+ imx_iomux_v3_setup_multiple_pads(
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+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
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+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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+ break;
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+ case 2:
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+ imx_iomux_v3_setup_multiple_pads(
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+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
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+ gpio_direction_input(USDHC4_CD_GPIO);
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+ usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
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+ break;
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+ default:
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+ printf("Warning: you configured more USDHC controllers\n"
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+ "(%d) then supported by the board (%d)\n",
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+ i + 1, CONFIG_SYS_FSL_USDHC_NUM);
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+ return -EINVAL;
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+ }
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+
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+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
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+ if (ret)
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+#endif
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+
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+static int mx6_rgmii_rework(struct phy_device *phydev)
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+{
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+ /* set device address 0x7 */
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
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+ /* offset 0x8016: CLK_25M Clock Select */
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
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+ /* enable register write, no post increment, address 0x7 */
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
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+ /* set to 125 MHz from local PLL source */
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
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+ /* set debug port address: SerDes Test and System Mode Control */
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
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+ /* enable rgmii tx clock delay */
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
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|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+int board_phy_config(struct phy_device *phydev)
|
|
|
+{
|
|
|
+ mx6_rgmii_rework(phydev);
|
|
|
+
|
|
|
+ if (phydev->drv->config)
|
|
|
+ phydev->drv->config(phydev);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+#if defined(CONFIG_VIDEO_IPUV3)
|
|
|
+static iomux_v3_cfg_t const backlight_pads[] = {
|
|
|
+ /* Power for LVDS Display */
|
|
|
+ MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
|
+#define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
|
|
|
+ /* Backlight enable for LVDS display */
|
|
|
+ MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
|
+#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
|
|
|
+ /* backlight PWM brightness control */
|
|
|
+ MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
|
+};
|
|
|
+
|
|
|
+static void do_enable_hdmi(struct display_info_t const *dev)
|
|
|
+{
|
|
|
+ imx_enable_hdmi_phy();
|
|
|
+}
|
|
|
+
|
|
|
+int board_cfb_skip(void)
|
|
|
+{
|
|
|
+ gpio_direction_output(LVDS_POWER_GP, 1);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int detect_baseboard(struct display_info_t const *dev)
|
|
|
+{
|
|
|
+ return 0 == dev->addr;
|
|
|
+}
|
|
|
+
|
|
|
+struct display_info_t const displays[] = {{
|
|
|
+ .bus = -1,
|
|
|
+ .addr = 0,
|
|
|
+ .pixfmt = IPU_PIX_FMT_RGB24,
|
|
|
+ .detect = detect_baseboard,
|
|
|
+ .enable = NULL,
|
|
|
+ .mode = {
|
|
|
+ .name = "SHARP-LQ156M1LG21",
|
|
|
+ .refresh = 60,
|
|
|
+ .xres = 1920,
|
|
|
+ .yres = 1080,
|
|
|
+ .pixclock = 7851,
|
|
|
+ .left_margin = 100,
|
|
|
+ .right_margin = 40,
|
|
|
+ .upper_margin = 30,
|
|
|
+ .lower_margin = 3,
|
|
|
+ .hsync_len = 10,
|
|
|
+ .vsync_len = 2,
|
|
|
+ .sync = FB_SYNC_EXT,
|
|
|
+ .vmode = FB_VMODE_NONINTERLACED
|
|
|
+} }, {
|
|
|
+ .bus = -1,
|
|
|
+ .addr = 3,
|
|
|
+ .pixfmt = IPU_PIX_FMT_RGB24,
|
|
|
+ .detect = detect_hdmi,
|
|
|
+ .enable = do_enable_hdmi,
|
|
|
+ .mode = {
|
|
|
+ .name = "HDMI",
|
|
|
+ .refresh = 60,
|
|
|
+ .xres = 1024,
|
|
|
+ .yres = 768,
|
|
|
+ .pixclock = 15385,
|
|
|
+ .left_margin = 220,
|
|
|
+ .right_margin = 40,
|
|
|
+ .upper_margin = 21,
|
|
|
+ .lower_margin = 7,
|
|
|
+ .hsync_len = 60,
|
|
|
+ .vsync_len = 10,
|
|
|
+ .sync = FB_SYNC_EXT,
|
|
|
+ .vmode = FB_VMODE_NONINTERLACED
|
|
|
+} } };
|
|
|
+size_t display_count = ARRAY_SIZE(displays);
|
|
|
+
|
|
|
+static void setup_display(void)
|
|
|
+{
|
|
|
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
|
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
|
|
+
|
|
|
+ clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
|
|
|
+
|
|
|
+ imx_setup_hdmi();
|
|
|
+
|
|
|
+ /* Set LDB_DI0 as clock source for IPU_DI0 */
|
|
|
+ clrsetbits_le32(&mxc_ccm->chsccdr,
|
|
|
+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
|
|
|
+ (CHSCCDR_CLK_SEL_LDB_DI0 <<
|
|
|
+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
|
|
|
+
|
|
|
+ /* Turn on IPU LDB DI0 clocks */
|
|
|
+ setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
|
|
|
+
|
|
|
+ enable_ipu_clock();
|
|
|
+
|
|
|
+ writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
|
|
|
+ IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
|
|
|
+ IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
|
|
|
+ IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
|
|
|
+ IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
|
|
|
+ IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
|
|
|
+ IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
|
|
|
+ IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
|
|
|
+ IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
|
|
|
+ IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
|
|
|
+ &iomux->gpr[2]);
|
|
|
+
|
|
|
+ clrsetbits_le32(&iomux->gpr[3],
|
|
|
+ IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
|
|
|
+ IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
|
|
|
+ IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
|
|
|
+ (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
|
|
|
+ IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
|
|
|
+
|
|
|
+ /* backlights off until needed */
|
|
|
+ imx_iomux_v3_setup_multiple_pads(backlight_pads,
|
|
|
+ ARRAY_SIZE(backlight_pads));
|
|
|
+
|
|
|
+ gpio_direction_input(LVDS_POWER_GP);
|
|
|
+ gpio_direction_input(LVDS_BACKLIGHT_GP);
|
|
|
+}
|
|
|
+#endif /* CONFIG_VIDEO_IPUV3 */
|
|
|
+
|
|
|
+/*
|
|
|
+ * Do not overwrite the console
|
|
|
+ * Use always serial for U-Boot console
|
|
|
+ */
|
|
|
+int overwrite_console(void)
|
|
|
+{
|
|
|
+ return 1;
|
|
|
+}
|
|
|
+
|
|
|
+int board_eth_init(bd_t *bis)
|
|
|
+{
|
|
|
+ setup_iomux_enet();
|
|
|
+ setup_pcie();
|
|
|
+
|
|
|
+ return cpu_eth_init(bis);
|
|
|
+}
|
|
|
+
|
|
|
+static iomux_v3_cfg_t const misc_pads[] = {
|
|
|
+ MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
|
|
+ MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL),
|
|
|
+ MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL),
|
|
|
+ MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL),
|
|
|
+ MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL),
|
|
|
+ MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL),
|
|
|
+ MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL),
|
|
|
+};
|
|
|
+#define SUS_S3_OUT IMX_GPIO_NR(4, 11)
|
|
|
+#define WIFI_EN IMX_GPIO_NR(6, 14)
|
|
|
+
|
|
|
+int setup_ba16_sata(void)
|
|
|
+{
|
|
|
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ ret = enable_sata_clock();
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ clrsetbits_le32(&iomuxc_regs->gpr[13],
|
|
|
+ IOMUXC_GPR13_SATA_MASK,
|
|
|
+ IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
|
|
|
+ |IOMUXC_GPR13_SATA_PHY_7_SATA2M
|
|
|
+ |IOMUXC_GPR13_SATA_SPEED_3G
|
|
|
+ |(1<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
|
|
|
+ |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
|
|
|
+ |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16
|
|
|
+ |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB
|
|
|
+ |IOMUXC_GPR13_SATA_PHY_2_TX_1P133V
|
|
|
+ |IOMUXC_GPR13_SATA_PHY_1_SLOW);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+int board_early_init_f(void)
|
|
|
+{
|
|
|
+ imx_iomux_v3_setup_multiple_pads(misc_pads,
|
|
|
+ ARRAY_SIZE(misc_pads));
|
|
|
+
|
|
|
+ setup_iomux_uart();
|
|
|
+
|
|
|
+#if defined(CONFIG_VIDEO_IPUV3)
|
|
|
+ /* Set LDB clock to PLL2 PFD0 */
|
|
|
+ select_ldb_di_clock_source(MXC_PLL2_PFD0_CLK);
|
|
|
+#endif
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+int board_init(void)
|
|
|
+{
|
|
|
+ gpio_direction_output(SUS_S3_OUT, 1);
|
|
|
+ gpio_direction_output(WIFI_EN, 1);
|
|
|
+#if defined(CONFIG_VIDEO_IPUV3)
|
|
|
+ setup_display();
|
|
|
+#endif
|
|
|
+ /* address of boot parameters */
|
|
|
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
|
|
+
|
|
|
+#ifdef CONFIG_MXC_SPI
|
|
|
+ setup_spi();
|
|
|
+#endif
|
|
|
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
|
|
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
|
|
|
+ setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+#ifdef CONFIG_CMD_BMODE
|
|
|
+static const struct boot_mode board_boot_modes[] = {
|
|
|
+ /* 4 bit bus width */
|
|
|
+ {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
|
|
|
+ {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
|
|
|
+ {NULL, 0},
|
|
|
+};
|
|
|
+#endif
|
|
|
+
|
|
|
+int board_late_init(void)
|
|
|
+{
|
|
|
+#ifdef CONFIG_CMD_BMODE
|
|
|
+ add_board_boot_modes(board_boot_modes);
|
|
|
+#endif
|
|
|
+ /*
|
|
|
+ * We need at least 200ms between power on and backlight on
|
|
|
+ * as per specifications from CHI MEI
|
|
|
+ */
|
|
|
+ mdelay(250);
|
|
|
+
|
|
|
+ /* enable backlight PWM 1 */
|
|
|
+ pwm_init(0, 0, 0);
|
|
|
+
|
|
|
+ /* duty cycle 5000000ns, period: 5000000ns */
|
|
|
+ pwm_config(0, 5000000, 5000000);
|
|
|
+
|
|
|
+ /* Backlight Power */
|
|
|
+ gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
|
|
|
+
|
|
|
+ pwm_enable(0);
|
|
|
+
|
|
|
+#ifdef CONFIG_CMD_SATA
|
|
|
+ setup_ba16_sata();
|
|
|
+#endif
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+int checkboard(void)
|
|
|
+{
|
|
|
+ printf("BOARD: %s\n", CONFIG_BOARD_NAME);
|
|
|
+ return 0;
|
|
|
+}
|