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@@ -1,6 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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+ * Copyright 2019 NXP
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*/
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#include <common.h>
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@@ -271,11 +272,24 @@ unsigned long get_board_ddr_clk(void)
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return 66666666;
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}
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-int select_i2c_ch_pca9547(u8 ch)
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+int select_i2c_ch_pca9547(u8 ch, int bus_num)
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{
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int ret;
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+#ifdef CONFIG_DM_I2C
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+ struct udevice *dev;
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+
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+ ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
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+ 1, &dev);
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+ if (ret) {
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+ printf("%s: Cannot find udev for a bus %d\n", __func__,
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+ bus_num);
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+ return ret;
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+ }
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+ ret = dm_i2c_write(dev, 0, &ch, 1);
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+#else
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ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
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+#endif
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if (ret) {
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puts("PCA: failed to select proper channel\n");
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return ret;
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@@ -290,8 +304,10 @@ int dram_init(void)
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* When resuming from deep sleep, the I2C channel may not be
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* in the default channel. So, switch to the default channel
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* before accessing DDR SPD.
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+ *
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+ * PCA9547 mount on I2C1 bus
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*/
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- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
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fsl_initdram();
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#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
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defined(CONFIG_SPL_BUILD)
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@@ -304,16 +320,83 @@ int dram_init(void)
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int i2c_multiplexer_select_vid_channel(u8 channel)
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{
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- return select_i2c_ch_pca9547(channel);
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+ return select_i2c_ch_pca9547(channel, 0);
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}
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void board_retimer_init(void)
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{
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u8 reg;
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+ int bus_num = 0;
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/* Retimer is connected to I2C1_CH7_CH5 */
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- select_i2c_ch_pca9547(I2C_MUX_CH7);
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+ select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num);
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reg = I2C_MUX_CH5;
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+#ifdef CONFIG_DM_I2C
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+ struct udevice *dev;
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+ int ret;
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+
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+ ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
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+ 1, &dev);
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+ if (ret) {
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+ printf("%s: Cannot find udev for a bus %d\n", __func__,
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+ bus_num);
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+ return;
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+ }
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+ dm_i2c_write(dev, 0, ®, 1);
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+
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+ /* Access to Control/Shared register */
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+ ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
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+ 1, &dev);
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+ if (ret) {
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+ printf("%s: Cannot find udev for a bus %d\n", __func__,
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+ bus_num);
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+ return;
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+ }
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+
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+ reg = 0x0;
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+ dm_i2c_write(dev, 0xff, ®, 1);
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+
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+ /* Read device revision and ID */
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+ dm_i2c_read(dev, 1, ®, 1);
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+ debug("Retimer version id = 0x%x\n", reg);
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+
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+ /* Enable Broadcast. All writes target all channel register sets */
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+ reg = 0x0c;
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+ dm_i2c_write(dev, 0xff, ®, 1);
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+
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+ /* Reset Channel Registers */
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+ dm_i2c_read(dev, 0, ®, 1);
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+ reg |= 0x4;
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+ dm_i2c_write(dev, 0, ®, 1);
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+
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+ /* Enable override divider select and Enable Override Output Mux */
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+ dm_i2c_read(dev, 9, ®, 1);
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+ reg |= 0x24;
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+ dm_i2c_write(dev, 9, ®, 1);
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+
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+ /* Select VCO Divider to full rate (000) */
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+ dm_i2c_read(dev, 0x18, ®, 1);
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+ reg &= 0x8f;
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+ dm_i2c_write(dev, 0x18, ®, 1);
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+
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+ /* Selects active PFD MUX Input as Re-timed Data (001) */
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+ dm_i2c_read(dev, 0x1e, ®, 1);
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+ reg &= 0x3f;
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+ reg |= 0x20;
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+ dm_i2c_write(dev, 0x1e, ®, 1);
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+
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+ /* Set data rate as 10.3125 Gbps */
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+ reg = 0x0;
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+ dm_i2c_write(dev, 0x60, ®, 1);
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+ reg = 0xb2;
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+ dm_i2c_write(dev, 0x61, ®, 1);
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+ reg = 0x90;
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+ dm_i2c_write(dev, 0x62, ®, 1);
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+ reg = 0xb3;
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+ dm_i2c_write(dev, 0x63, ®, 1);
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+ reg = 0xcd;
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+ dm_i2c_write(dev, 0x64, ®, 1);
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+#else
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i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1);
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/* Access to Control/Shared register */
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@@ -360,9 +443,10 @@ void board_retimer_init(void)
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i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
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reg = 0xcd;
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i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
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+#endif
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/* Return the default channel */
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- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num);
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}
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int board_early_init_f(void)
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@@ -375,8 +459,10 @@ int board_early_init_f(void)
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u8 uart;
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#endif
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+#ifdef CONFIG_SYS_I2C
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#ifdef CONFIG_SYS_I2C_EARLY_INIT
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i2c_early_init_f();
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+#endif
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#endif
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fsl_lsch2_early_init_f();
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@@ -457,7 +543,7 @@ int board_init(void)
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erratum_a010315();
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#endif
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- select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
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board_retimer_init();
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#ifdef CONFIG_SYS_FSL_SERDES
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