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@@ -10,6 +10,7 @@
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#include <common.h>
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#include <asm/arch/cpu.h>
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+#include <asm/arch/sys_proto.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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@@ -55,26 +56,94 @@ struct dpll_params dpll_mpu_opp100 = {
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CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
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const struct dpll_params dpll_core_opp100 = {
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1000, OSC-1, -1, -1, 10, 8, 4};
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-const struct dpll_params dpll_mpu = {
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- MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
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-const struct dpll_params dpll_core = {
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- 50, OSC-1, -1, -1, 1, 1, 1};
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-const struct dpll_params dpll_per = {
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- 960, OSC-1, 5, -1, -1, -1, -1};
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-
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-const struct dpll_params *get_dpll_mpu_params(void)
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+
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+const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
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+ { /* 19.2 MHz */
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+ {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
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+ {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
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+ {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */
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+ {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */
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+ {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */
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+ {625, 11, 1, -1, -1, -1, -1} /* OPP NT */
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+ },
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+ { /* 24 MHz */
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+ {25, 0, 2, -1, -1, -1, -1}, /* OPP 50 */
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+ {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
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+ {25, 0, 1, -1, -1, -1, -1}, /* OPP 100 */
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+ {30, 0, 1, -1, -1, -1, -1}, /* OPP 120 */
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+ {100, 3, 1, -1, -1, -1, -1}, /* OPP TB */
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+ {125, 2, 1, -1, -1, -1, -1} /* OPP NT */
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+ },
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+ { /* 25 MHz */
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+ {24, 0, 2, -1, -1, -1, -1}, /* OPP 50 */
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+ {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
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+ {24, 0, 1, -1, -1, -1, -1}, /* OPP 100 */
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+ {144, 4, 1, -1, -1, -1, -1}, /* OPP 120 */
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+ {32, 0, 1, -1, -1, -1, -1}, /* OPP TB */
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+ {40, 0, 1, -1, -1, -1, -1} /* OPP NT */
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+ },
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+ { /* 26 MHz */
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+ {300, 12, 2, -1, -1, -1, -1}, /* OPP 50 */
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+ {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
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+ {300, 12, 1, -1, -1, -1, -1}, /* OPP 100 */
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+ {360, 12, 1, -1, -1, -1, -1}, /* OPP 120 */
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+ {400, 12, 1, -1, -1, -1, -1}, /* OPP TB */
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+ {500, 12, 1, -1, -1, -1, -1} /* OPP NT */
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+ },
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+};
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+
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+const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ] = {
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+ {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
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+ {125, 2, -1, -1, 10, 8, 4}, /* 24 MHz */
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+ {40, 0, -1, -1, 10, 8, 4}, /* 25 MHz */
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+ {500, 12, -1, -1, 10, 8, 4} /* 26 MHz */
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+};
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+
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+const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ] = {
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+ {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */
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+ {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */
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+ {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */
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+ {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */
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+};
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+
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+const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ] = {
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+ {505, 15, 2, -1, -1, -1, -1}, /*19.2*/
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+ {101, 3, 2, -1, -1, -1, -1}, /* 24 MHz */
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+ {303, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
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+ {303, 12, 2, -1, 4, -1, -1} /* 26 MHz */
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+};
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+
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+const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ] = {
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+ {125, 5, 1, -1, -1, -1, -1}, /*19.2*/
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+ {50, 2, 1, -1, -1, -1, -1}, /* 24 MHz */
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+ {16, 0, 1, -1, 4, -1, -1}, /* 25 MHz */
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+ {200, 12, 1, -1, 4, -1, -1} /* 26 MHz */
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+};
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+
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+const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ] = {
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+ {665, 47, 1, -1, -1, -1, -1}, /*19.2*/
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+ {133, 11, 1, -1, -1, -1, -1}, /* 24 MHz */
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+ {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */
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+ {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */
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+};
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+
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+__weak const struct dpll_params *get_dpll_mpu_params(void)
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{
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- return &dpll_mpu;
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+ return &dpll_mpu_opp100;
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}
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const struct dpll_params *get_dpll_core_params(void)
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{
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- return &dpll_core;
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+ int ind = get_sys_clk_index();
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+
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+ return &dpll_core_1000MHz[ind];
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}
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const struct dpll_params *get_dpll_per_params(void)
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{
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- return &dpll_per;
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+ int ind = get_sys_clk_index();
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+
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+ return &dpll_per_192MHz[ind];
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}
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void setup_clocks_for_console(void)
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