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@@ -0,0 +1,426 @@
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+/*
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+ * Copyright (C) 2016 Stefano Babic <sbabic@denx.de>
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+ *
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+ * SPDX-License-Identifier: GPL-2.0+
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+ */
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+
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+#include <asm/arch/clock.h>
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+#include <asm/arch/imx-regs.h>
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+#include <asm/arch/iomux.h>
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+#include <asm/arch/mx6-pins.h>
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+#include <linux/errno.h>
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+#include <asm/gpio.h>
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+#include <asm/mach-imx/iomux-v3.h>
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+#include <asm/mach-imx/video.h>
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+#include <mmc.h>
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+#include <fsl_esdhc.h>
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+#include <asm/arch/crm_regs.h>
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+#include <asm/io.h>
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+#include <asm/arch/sys_proto.h>
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+#include <spl.h>
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+#include <netdev.h>
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+#include <miiphy.h>
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+#include <micrel.h>
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+
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+#include <common.h>
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+#include <malloc.h>
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+#include <fuse.h>
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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+
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+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
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+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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+
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+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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+
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+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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+
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+static iomux_v3_cfg_t const uart1_pads[] = {
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+ IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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+ IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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+};
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+
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+static iomux_v3_cfg_t const gpios_pads[] = {
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+ IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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+};
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+
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+static iomux_v3_cfg_t const usdhc2_pads[] = {
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+ IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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+ IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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+ IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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+ IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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+ IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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+ IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
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+ IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
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+};
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+
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+static iomux_v3_cfg_t const enet_pads[] = {
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+ IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
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+ MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
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+ MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
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+ MUX_PAD_CTRL(ENET_PAD_CTRL)),
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+ IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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+};
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+
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+iomux_v3_cfg_t const enet_pads1[] = {
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+ /* pin 35 - 1 (PHY_AD2) on reset */
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+ IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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+ /* pin 32 - 1 - (MODE0) all */
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+ IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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+ /* pin 31 - 1 - (MODE1) all */
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+ IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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+ /* pin 28 - 1 - (MODE2) all */
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+ IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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+ /* pin 27 - 1 - (MODE3) all */
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+ IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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+ /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
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+ IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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+ /* pin 42 PHY nRST */
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+ IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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+};
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+
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+static int mx6_rgmii_rework(struct phy_device *phydev)
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+{
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+
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+ /* min rx data delay */
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+ ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
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+ 0x0);
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+ /* min tx data delay */
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+ ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
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+ 0x0);
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+ /* max rx/tx clock delay, min rx/tx control */
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+ ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
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+ 0xf0f0);
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+
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+ return 0;
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+}
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+
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+int board_phy_config(struct phy_device *phydev)
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+{
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+ mx6_rgmii_rework(phydev);
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+
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+ if (phydev->drv->config)
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+ return phydev->drv->config(phydev);
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+
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+ return 0;
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+}
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+
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+#define ENET_NRST IMX_GPIO_NR(1, 25)
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+
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+void setup_iomux_enet(void)
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+{
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+ SETUP_IOMUX_PADS(enet_pads);
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+
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+}
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+
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+int board_eth_init(bd_t *bis)
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+{
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+ uint32_t base = IMX_FEC_BASE;
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+ struct mii_dev *bus = NULL;
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+ struct phy_device *phydev = NULL;
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+ int ret;
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+
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+ setup_iomux_enet();
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+
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+ bus = fec_get_miibus(base, -1);
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+ if (!bus)
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+ return -EINVAL;
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+ /* scan phy */
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+ phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
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+ PHY_INTERFACE_MODE_RGMII);
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+
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+ if (!phydev) {
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+ ret = -EINVAL;
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+ goto free_bus;
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+ }
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+ ret = fec_probe(bis, -1, base, bus, phydev);
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+ if (ret)
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+ goto free_phydev;
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+
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+ return 0;
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+
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+free_phydev:
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+ free(phydev);
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+free_bus:
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+ free(bus);
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+ return ret;
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+}
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+
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+int board_early_init_f(void)
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+{
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+ SETUP_IOMUX_PADS(uart1_pads);
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+
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+ return 0;
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+}
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+
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+int board_init(void)
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+{
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+ /* Address of boot parameters */
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+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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+
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+ /* Take in reset the ATMega processor */
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+ SETUP_IOMUX_PADS(gpios_pads);
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+ gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
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+
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+ return 0;
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+}
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+
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+int dram_init(void)
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+{
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+ gd->ram_size = imx_ddr_size();
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+
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+ return 0;
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+}
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+
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+struct fsl_esdhc_cfg usdhc_cfg[1] = {
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+ {USDHC2_BASE_ADDR, 0},
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+};
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+
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+#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 0)
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+int board_mmc_getcd(struct mmc *mmc)
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+{
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+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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+ int ret = 0;
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+
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+ if (cfg->esdhc_base == USDHC2_BASE_ADDR)
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+ ret = 1;
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+
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+ return ret;
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+}
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+
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+int board_mmc_init(bd_t *bis)
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+{
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+ int ret;
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+
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+ SETUP_IOMUX_PADS(usdhc2_pads);
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+ gpio_direction_input(USDHC2_CD_GPIO);
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+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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+ usdhc_cfg[0].max_bus_width = 4;
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+
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+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
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+ if (ret) {
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+ printf("Warning: failed to initialize mmc dev \n");
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+
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+#if defined(CONFIG_SPL_BUILD)
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+#include <asm/arch/mx6-ddr.h>
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+
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+/*
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+ * Driving strength:
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+ * 0x30 == 40 Ohm
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+ * 0x28 == 48 Ohm
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+ */
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+#define IMX6SDL_DRIVE_STRENGTH 0x230
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+
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+
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+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
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+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
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+ .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_cas = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_ras = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_reset = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdba2 = 0x00000000,
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+ .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
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+ .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
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+};
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+
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+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
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+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
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+ .grp_ddr_type = 0x000c0000,
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+ .grp_ddrmode_ctl = 0x00020000,
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+ .grp_ddrpke = 0x00000000,
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+ .grp_addds = IMX6SDL_DRIVE_STRENGTH,
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+ .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
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+ .grp_ddrmode = 0x00020000,
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+ .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
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+ .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
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+ .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
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+ .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
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+ .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
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+ .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
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+ .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
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+ .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
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+};
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+
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+/* MT41K128M16JT-125 */
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+static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
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+ /* quad = 1066, duallite = 800 */
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+ .mem_speed = 1066,
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+ .density = 2,
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+ .width = 16,
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+ .banks = 8,
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+ .rowaddr = 14,
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+ .coladdr = 10,
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+ .pagesz = 2,
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+ .trcd = 1375,
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+ .trcmin = 4875,
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+ .trasmin = 3500,
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+ .SRT = 0,
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+};
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+
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+static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
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+ .p0_mpwldectrl0 = 0x0043004E,
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+ .p0_mpwldectrl1 = 0x003D003F,
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+ .p1_mpwldectrl0 = 0x00230021,
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+ .p1_mpwldectrl1 = 0x0028003E,
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+ .p0_mpdgctrl0 = 0x42580250,
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+ .p0_mpdgctrl1 = 0x0238023C,
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+ .p1_mpdgctrl0 = 0x422C0238,
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+ .p1_mpdgctrl1 = 0x02180228,
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+ .p0_mprddlctl = 0x44464A46,
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+ .p1_mprddlctl = 0x44464A42,
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+ .p0_mpwrdlctl = 0x36343236,
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+ .p1_mpwrdlctl = 0x36343230,
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+};
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+
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+/* DDR 64bit 1GB */
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+static struct mx6_ddr_sysinfo mem_qdl = {
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+ .dsize = 2,
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+ .cs1_mirror = 0,
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+ /* config for full 4GB range so that get_mem_size() works */
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+ .cs_density = 32,
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+ .ncs = 1,
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+ .bi_on = 1,
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+ .rtt_nom = 1,
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+ .rtt_wr = 1,
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+ .ralat = 5,
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+ .walat = 0,
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+ .mif3_mode = 3,
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+ .rst_to_cke = 0x23,
|
|
|
+ .sde_to_rst = 0x10,
|
|
|
+ .refsel = 1, /* Refresh cycles at 32KHz */
|
|
|
+ .refr = 7, /* 8 refresh commands per refresh cycle */
|
|
|
+};
|
|
|
+
|
|
|
+static void ccgr_init(void)
|
|
|
+{
|
|
|
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
|
+
|
|
|
+ /* set the default clock gate to save power */
|
|
|
+ writel(0x00C03F3F, &ccm->CCGR0);
|
|
|
+ writel(0x0030FC03, &ccm->CCGR1);
|
|
|
+ writel(0x0FFFC000, &ccm->CCGR2);
|
|
|
+ writel(0x3FF00000, &ccm->CCGR3);
|
|
|
+ writel(0x00FFF300, &ccm->CCGR4);
|
|
|
+ writel(0xFFFFFFFF, &ccm->CCGR5);
|
|
|
+ writel(0x000003FF, &ccm->CCGR6);
|
|
|
+}
|
|
|
+
|
|
|
+static void spl_dram_init(void)
|
|
|
+{
|
|
|
+ if (is_cpu_type(MXC_CPU_MX6DL)) {
|
|
|
+ mt41k128m16jt_125.mem_speed = 800;
|
|
|
+ mem_qdl.rtt_nom = 1;
|
|
|
+ mem_qdl.rtt_wr = 1;
|
|
|
+
|
|
|
+ mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
|
|
|
+ mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125);
|
|
|
+ } else {
|
|
|
+ printf("Wrong CPU for this board\n");
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ udelay(100);
|
|
|
+
|
|
|
+#ifdef CONFIG_MX6_DDRCAL
|
|
|
+
|
|
|
+ /* Perform DDR DRAM calibration */
|
|
|
+ mmdc_do_write_level_calibration(&mem_qdl);
|
|
|
+ mmdc_do_dqs_calibration(&mem_qdl);
|
|
|
+#endif
|
|
|
+}
|
|
|
+
|
|
|
+static void check_bootcfg(void)
|
|
|
+{
|
|
|
+ u32 val5, val6;
|
|
|
+
|
|
|
+ fuse_sense(0, 5, &val5);
|
|
|
+ fuse_sense(0, 6, &val6);
|
|
|
+ /* Check if boot from MMC */
|
|
|
+ if (val6 & 0x10) {
|
|
|
+ puts("BT_FUSE_SEL already fused, will do nothing\n");
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ fuse_prog(0, 5, 0x00000840);
|
|
|
+ /* BT_FUSE_SEL */
|
|
|
+ fuse_prog(0, 6, 0x00000010);
|
|
|
+
|
|
|
+ do_reset(NULL, 0, 0, NULL);
|
|
|
+}
|
|
|
+
|
|
|
+void board_init_f(ulong dummy)
|
|
|
+{
|
|
|
+ ccgr_init();
|
|
|
+
|
|
|
+ /* setup AIPS and disable watchdog */
|
|
|
+ arch_cpu_init();
|
|
|
+
|
|
|
+ gpr_init();
|
|
|
+
|
|
|
+ /* iomux */
|
|
|
+ board_early_init_f();
|
|
|
+
|
|
|
+ /* setup GP timer */
|
|
|
+ timer_init();
|
|
|
+
|
|
|
+ /* UART clocks enabled and gd valid - init serial console */
|
|
|
+ preloader_console_init();
|
|
|
+
|
|
|
+ /* DDR initialization */
|
|
|
+ spl_dram_init();
|
|
|
+
|
|
|
+ /* Set fuses for new boards and reboot if not set */
|
|
|
+ check_bootcfg();
|
|
|
+
|
|
|
+ /* Clear the BSS. */
|
|
|
+ memset(__bss_start, 0, __bss_end - __bss_start);
|
|
|
+
|
|
|
+ /* load/boot image from boot device */
|
|
|
+ board_init_r(NULL, 0);
|
|
|
+}
|
|
|
+#endif
|