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@@ -42,8 +42,9 @@
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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+#include <dt-bindings/clock/sun50i-a64-ccu.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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-#include <dt-bindings/pinctrl/sun4i-a10.h>
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+#include <dt-bindings/reset/sun50i-a64-ccu.h>
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/ {
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interrupt-parent = <&gic>;
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@@ -54,28 +55,28 @@
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#address-cells = <1>;
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#size-cells = <0>;
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- cpu@0 {
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+ cpu0: cpu@0 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0>;
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enable-method = "psci";
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};
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- cpu@1 {
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+ cpu1: cpu@1 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <1>;
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enable-method = "psci";
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};
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- cpu@2 {
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+ cpu2: cpu@2 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <2>;
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enable-method = "psci";
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};
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- cpu@3 {
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+ cpu3: cpu@3 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <3>;
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@@ -83,28 +84,31 @@
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};
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};
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- psci {
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- compatible = "arm,psci-0.2";
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- method = "smc";
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+ osc24M: osc24M_clk {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ clock-frequency = <24000000>;
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+ clock-output-names = "osc24M";
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+ };
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+
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+ osc32k: osc32k_clk {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ clock-frequency = <32768>;
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+ clock-output-names = "osc32k";
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};
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- memory {
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- device_type = "memory";
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- reg = <0x40000000 0>;
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+ iosc: internal-osc-clk {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ clock-frequency = <16000000>;
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+ clock-accuracy = <300000000>;
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+ clock-output-names = "iosc";
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};
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- gic: interrupt-controller@1c81000 {
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- compatible = "arm,gic-400";
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- interrupt-controller;
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- #interrupt-cells = <3>;
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- #address-cells = <0>;
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-
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- reg = <0x01c81000 0x1000>,
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- <0x01c82000 0x2000>,
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- <0x01c84000 0x2000>,
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- <0x01c86000 0x2000>;
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- interrupts = <GIC_PPI 9
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- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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+ psci {
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+ compatible = "arm,psci-0.2";
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+ method = "smc";
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};
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timer {
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@@ -119,199 +123,6 @@
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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- clocks {
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- #address-cells = <1>;
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- #size-cells = <1>;
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- ranges;
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-
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- osc24M: osc24M_clk {
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- #clock-cells = <0>;
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- compatible = "fixed-clock";
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- clock-frequency = <24000000>;
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- clock-output-names = "osc24M";
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- };
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-
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- osc32k: osc32k_clk {
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- #clock-cells = <0>;
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- compatible = "fixed-clock";
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- clock-frequency = <32768>;
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- clock-output-names = "osc32k";
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- };
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-
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- pll1: pll1_clk@1c20000 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun8i-a23-pll1-clk";
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- reg = <0x01c20000 0x4>;
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- clocks = <&osc24M>;
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- clock-output-names = "pll1";
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- };
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-
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- pll6: pll6_clk@1c20028 {
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- #clock-cells = <1>;
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- compatible = "allwinner,sun6i-a31-pll6-clk";
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- reg = <0x01c20028 0x4>;
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- clocks = <&osc24M>;
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- clock-output-names = "pll6", "pll6x2";
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- };
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-
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- pll6d2: pll6d2_clk {
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- #clock-cells = <0>;
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- compatible = "fixed-factor-clock";
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- clock-div = <2>;
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- clock-mult = <1>;
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- clocks = <&pll6 0>;
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- clock-output-names = "pll6d2";
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- };
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-
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- pll7: pll7_clk@1c2002c {
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- #clock-cells = <1>;
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- compatible = "allwinner,sun6i-a31-pll6-clk";
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- reg = <0x01c2002c 0x4>;
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- clocks = <&osc24M>;
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- clock-output-names = "pll7", "pll7x2";
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- };
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-
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- cpu: cpu_clk@1c20050 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-cpu-clk";
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- reg = <0x01c20050 0x4>;
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- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
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- clock-output-names = "cpu";
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- critical-clocks = <0>;
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- };
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-
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- axi: axi_clk@1c20050 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-axi-clk";
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- reg = <0x01c20050 0x4>;
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- clocks = <&cpu>;
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- clock-output-names = "axi";
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- };
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-
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- ahb1: ahb1_clk@1c20054 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun6i-a31-ahb1-clk";
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- reg = <0x01c20054 0x4>;
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- clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
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- clock-output-names = "ahb1";
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- };
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-
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- ahb2: ahb2_clk@1c2005c {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun8i-h3-ahb2-clk";
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- reg = <0x01c2005c 0x4>;
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- clocks = <&ahb1>, <&pll6d2>;
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- clock-output-names = "ahb2";
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- };
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-
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- apb1: apb1_clk@1c20054 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-apb0-clk";
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- reg = <0x01c20054 0x4>;
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- clocks = <&ahb1>;
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- clock-output-names = "apb1";
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- };
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-
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- apb2: apb2_clk@1c20058 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-apb1-clk";
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- reg = <0x01c20058 0x4>;
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- clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
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- clock-output-names = "apb2";
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- };
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-
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- bus_gates: bus_gates_clk@1c20060 {
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- #clock-cells = <1>;
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- compatible = "allwinner,sun50i-a64-bus-gates-clk",
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- "allwinner,sunxi-multi-bus-gates-clk";
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- reg = <0x01c20060 0x14>;
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- ahb1_parent {
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- clocks = <&ahb1>;
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- clock-indices = <1>, <5>,
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- <6>, <8>,
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- <9>, <10>,
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- <13>, <14>,
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- <18>, <19>,
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- <20>, <21>,
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- <23>, <24>,
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- <25>, <28>,
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- <32>, <35>,
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- <36>, <37>,
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- <40>, <43>,
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- <44>, <52>,
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- <53>, <54>,
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- <135>;
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- clock-output-names = "bus_mipidsi", "bus_ce",
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- "bus_dma", "bus_mmc0",
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- "bus_mmc1", "bus_mmc2",
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- "bus_nand", "bus_sdram",
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- "bus_ts", "bus_hstimer",
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- "bus_spi0", "bus_spi1",
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- "bus_otg", "bus_otg_ehci0",
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- "bus_ehci0", "bus_otg_ohci0",
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- "bus_ve", "bus_lcd0",
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- "bus_lcd1", "bus_deint",
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- "bus_csi", "bus_hdmi",
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- "bus_de", "bus_gpu",
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- "bus_msgbox", "bus_spinlock",
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- "bus_dbg";
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- };
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- ahb2_parent {
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- clocks = <&ahb2>;
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- clock-indices = <17>, <29>;
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- clock-output-names = "bus_gmac", "bus_ohci0";
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- };
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- apb1_parent {
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- clocks = <&apb1>;
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- clock-indices = <64>, <65>,
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- <69>, <72>,
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- <76>, <77>,
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- <78>;
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- clock-output-names = "bus_codec", "bus_spdif",
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- "bus_pio", "bus_ths",
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- "bus_i2s0", "bus_i2s1",
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- "bus_i2s2";
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- };
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- abp2_parent {
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- clocks = <&apb2>;
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- clock-indices = <96>, <97>,
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- <98>, <101>,
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- <112>, <113>,
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- <114>, <115>,
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- <116>;
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- clock-output-names = "bus_i2c0", "bus_i2c1",
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- "bus_i2c2", "bus_scr",
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- "bus_uart0", "bus_uart1",
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- "bus_uart2", "bus_uart3",
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- "bus_uart4";
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- };
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- };
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-
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- mmc0_clk: mmc0_clk@1c20088 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-mod0-clk";
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- reg = <0x01c20088 0x4>;
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- clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
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- clock-output-names = "mmc0";
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- };
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-
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- mmc1_clk: mmc1_clk@1c2008c {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-mod0-clk";
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- reg = <0x01c2008c 0x4>;
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- clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
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- clock-output-names = "mmc1";
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- };
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-
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- mmc2_clk: mmc2_clk@1c20090 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-mod0-clk";
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- reg = <0x01c20090 0x4>;
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- clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
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- clock-output-names = "mmc2";
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- };
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- };
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-
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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@@ -319,240 +130,181 @@
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ranges;
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mmc0: mmc@1c0f000 {
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- compatible = "allwinner,sun50i-a64-mmc",
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- "allwinner,sun5i-a13-mmc";
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+ compatible = "allwinner,sun50i-a64-mmc";
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reg = <0x01c0f000 0x1000>;
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- clocks = <&bus_gates 8>, <&mmc0_clk>,
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- <&mmc0_clk>, <&mmc0_clk>;
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- clock-names = "ahb", "mmc",
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- "output", "sample";
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- resets = <&ahb_rst 8>;
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+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
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+ clock-names = "ahb", "mmc";
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+ resets = <&ccu RST_BUS_MMC0>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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+ max-frequency = <150000000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc1: mmc@1c10000 {
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- compatible = "allwinner,sun50i-a64-mmc",
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- "allwinner,sun5i-a13-mmc";
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+ compatible = "allwinner,sun50i-a64-mmc";
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reg = <0x01c10000 0x1000>;
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- clocks = <&bus_gates 9>, <&mmc1_clk>,
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- <&mmc1_clk>, <&mmc1_clk>;
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- clock-names = "ahb", "mmc",
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- "output", "sample";
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- resets = <&ahb_rst 9>;
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+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
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+ clock-names = "ahb", "mmc";
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+ resets = <&ccu RST_BUS_MMC1>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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+ max-frequency = <150000000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc2: mmc@1c11000 {
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- compatible = "allwinner,sun50i-a64-mmc",
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- "allwinner,sun5i-a13-mmc";
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+ compatible = "allwinner,sun50i-a64-emmc";
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reg = <0x01c11000 0x1000>;
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- clocks = <&bus_gates 10>, <&mmc2_clk>,
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- <&mmc2_clk>, <&mmc2_clk>;
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- clock-names = "ahb", "mmc",
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- "output", "sample";
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- resets = <&ahb_rst 10>;
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+ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
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+ clock-names = "ahb", "mmc";
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+ resets = <&ccu RST_BUS_MMC2>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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+ max-frequency = <200000000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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+ usb_otg: usb@01c19000 {
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+ compatible = "allwinner,sun8i-a33-musb";
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+ reg = <0x01c19000 0x0400>;
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+ clocks = <&ccu CLK_BUS_OTG>;
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+ resets = <&ccu RST_BUS_OTG>;
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+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "mc";
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+ phys = <&usbphy 0>;
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+ phy-names = "usb";
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+ extcon = <&usbphy 0>;
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+ status = "disabled";
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+ };
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+
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+ usbphy: phy@01c19400 {
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+ compatible = "allwinner,sun50i-a64-usb-phy";
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+ reg = <0x01c19400 0x14>,
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+ <0x01c1a800 0x4>,
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+ <0x01c1b800 0x4>;
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+ reg-names = "phy_ctrl",
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+ "pmu0",
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+ "pmu1";
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+ clocks = <&ccu CLK_USB_PHY0>,
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+ <&ccu CLK_USB_PHY1>;
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+ clock-names = "usb0_phy",
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+ "usb1_phy";
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+ resets = <&ccu RST_USB_PHY0>,
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+ <&ccu RST_USB_PHY1>;
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+ reset-names = "usb0_reset",
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+ "usb1_reset";
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+ status = "disabled";
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+ #phy-cells = <1>;
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+ };
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+
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+ ehci1: usb@01c1b000 {
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|
|
+ compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
|
|
|
+ reg = <0x01c1b000 0x100>;
|
|
|
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&ccu CLK_BUS_OHCI1>,
|
|
|
+ <&ccu CLK_BUS_EHCI1>,
|
|
|
+ <&ccu CLK_USB_OHCI1>;
|
|
|
+ resets = <&ccu RST_BUS_OHCI1>,
|
|
|
+ <&ccu RST_BUS_EHCI1>;
|
|
|
+ phys = <&usbphy 1>;
|
|
|
+ phy-names = "usb";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ ohci1: usb@01c1b400 {
|
|
|
+ compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
|
|
|
+ reg = <0x01c1b400 0x100>;
|
|
|
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&ccu CLK_BUS_OHCI1>,
|
|
|
+ <&ccu CLK_USB_OHCI1>;
|
|
|
+ resets = <&ccu RST_BUS_OHCI1>;
|
|
|
+ phys = <&usbphy 1>;
|
|
|
+ phy-names = "usb";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ ccu: clock@01c20000 {
|
|
|
+ compatible = "allwinner,sun50i-a64-ccu";
|
|
|
+ reg = <0x01c20000 0x400>;
|
|
|
+ clocks = <&osc24M>, <&osc32k>;
|
|
|
+ clock-names = "hosc", "losc";
|
|
|
+ #clock-cells = <1>;
|
|
|
+ #reset-cells = <1>;
|
|
|
+ };
|
|
|
+
|
|
|
pio: pinctrl@1c20800 {
|
|
|
compatible = "allwinner,sun50i-a64-pinctrl";
|
|
|
reg = <0x01c20800 0x400>;
|
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
- clocks = <&bus_gates 69>;
|
|
|
+ clocks = <&ccu 58>;
|
|
|
gpio-controller;
|
|
|
#gpio-cells = <3>;
|
|
|
interrupt-controller;
|
|
|
- #interrupt-cells = <2>;
|
|
|
-
|
|
|
- uart0_pins_a: uart0@0 {
|
|
|
- allwinner,pins = "PB8", "PB9";
|
|
|
- allwinner,function = "uart0";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
- };
|
|
|
-
|
|
|
- uart0_pins_b: uart0@1 {
|
|
|
- allwinner,pins = "PF2", "PF3";
|
|
|
- allwinner,function = "uart0";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
- };
|
|
|
-
|
|
|
- uart1_2pins: uart1_2@0 {
|
|
|
- allwinner,pins = "PG6", "PG7";
|
|
|
- allwinner,function = "uart1";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
- };
|
|
|
-
|
|
|
- uart1_4pins: uart1_4@0 {
|
|
|
- allwinner,pins = "PG6", "PG7", "PG8", "PG9";
|
|
|
- allwinner,function = "uart1";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
- };
|
|
|
-
|
|
|
- uart2_2pins: uart2_2@0 {
|
|
|
- allwinner,pins = "PB0", "PB1";
|
|
|
- allwinner,function = "uart2";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
- };
|
|
|
-
|
|
|
- uart2_4pins: uart2_4@0 {
|
|
|
- allwinner,pins = "PB0", "PB1", "PB2", "PB3";
|
|
|
- allwinner,function = "uart2";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
- };
|
|
|
-
|
|
|
- uart3_pins_a: uart3@0 {
|
|
|
- allwinner,pins = "PD0", "PD1";
|
|
|
- allwinner,function = "uart3";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
- };
|
|
|
-
|
|
|
- uart3_2pins_b: uart3_2@1 {
|
|
|
- allwinner,pins = "PH4", "PH5";
|
|
|
- allwinner,function = "uart3";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
- };
|
|
|
+ #interrupt-cells = <3>;
|
|
|
|
|
|
- uart3_4pins_b: uart3_4@1 {
|
|
|
- allwinner,pins = "PH4", "PH5", "PH6", "PH7";
|
|
|
- allwinner,function = "uart3";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
- };
|
|
|
-
|
|
|
- uart4_2pins: uart4_2@0 {
|
|
|
- allwinner,pins = "PD2", "PD3";
|
|
|
- allwinner,function = "uart4";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
- };
|
|
|
-
|
|
|
- uart4_4pins: uart4_4@0 {
|
|
|
- allwinner,pins = "PD2", "PD3", "PD4", "PD5";
|
|
|
- allwinner,function = "uart4";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
- };
|
|
|
-
|
|
|
- mmc0_pins: mmc0@0 {
|
|
|
- allwinner,pins = "PF0", "PF1", "PF2", "PF3",
|
|
|
- "PF4", "PF5";
|
|
|
- allwinner,function = "mmc0";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
- };
|
|
|
-
|
|
|
- mmc0_default_cd_pin: mmc0_cd_pin@0 {
|
|
|
- allwinner,pins = "PF6";
|
|
|
- allwinner,function = "gpio_in";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
|
|
|
- };
|
|
|
-
|
|
|
- mmc1_pins: mmc1@0 {
|
|
|
- allwinner,pins = "PG0", "PG1", "PG2", "PG3",
|
|
|
- "PG4", "PG5";
|
|
|
- allwinner,function = "mmc1";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ i2c1_pins: i2c1_pins {
|
|
|
+ pins = "PH2", "PH3";
|
|
|
+ function = "i2c1";
|
|
|
};
|
|
|
|
|
|
- mmc2_pins: mmc2@0 {
|
|
|
- allwinner,pins = "PC1", "PC5", "PC6", "PC8",
|
|
|
- "PC9", "PC10";
|
|
|
- allwinner,function = "mmc2";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ mmc0_pins: mmc0-pins {
|
|
|
+ pins = "PF0", "PF1", "PF2", "PF3",
|
|
|
+ "PF4", "PF5";
|
|
|
+ function = "mmc0";
|
|
|
+ drive-strength = <30>;
|
|
|
+ bias-pull-up;
|
|
|
};
|
|
|
|
|
|
- i2c0_pins: i2c0_pins {
|
|
|
- allwinner,pins = "PH0", "PH1";
|
|
|
- allwinner,function = "i2c0";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ mmc1_pins: mmc1-pins {
|
|
|
+ pins = "PG0", "PG1", "PG2", "PG3",
|
|
|
+ "PG4", "PG5";
|
|
|
+ function = "mmc1";
|
|
|
+ drive-strength = <30>;
|
|
|
+ bias-pull-up;
|
|
|
};
|
|
|
|
|
|
- i2c1_pins: i2c1_pins {
|
|
|
- allwinner,pins = "PH2", "PH3";
|
|
|
- allwinner,function = "i2c1";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ mmc2_pins: mmc2-pins {
|
|
|
+ pins = "PC1", "PC5", "PC6", "PC8", "PC9",
|
|
|
+ "PC10","PC11", "PC12", "PC13",
|
|
|
+ "PC14", "PC15", "PC16";
|
|
|
+ function = "mmc2";
|
|
|
+ drive-strength = <30>;
|
|
|
+ bias-pull-up;
|
|
|
};
|
|
|
|
|
|
- i2c2_pins: i2c2_pins {
|
|
|
- allwinner,pins = "PE14", "PE15";
|
|
|
- allwinner,function = "i2c2";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ uart0_pins_a: uart0@0 {
|
|
|
+ pins = "PB8", "PB9";
|
|
|
+ function = "uart0";
|
|
|
};
|
|
|
|
|
|
- rmii_pins: rmii_pins {
|
|
|
- allwinner,pins = "PD10", "PD11", "PD13", "PD14",
|
|
|
- "PD17", "PD18", "PD19", "PD20",
|
|
|
- "PD22", "PD23";
|
|
|
- allwinner,function = "emac";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_40_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ uart1_pins: uart1_pins {
|
|
|
+ pins = "PG6", "PG7";
|
|
|
+ function = "uart1";
|
|
|
};
|
|
|
|
|
|
- rgmii_pins: rgmii_pins {
|
|
|
- allwinner,pins = "PD8", "PD9", "PD10", "PD11",
|
|
|
- "PD12", "PD13", "PD15",
|
|
|
- "PD16", "PD17", "PD18", "PD19",
|
|
|
- "PD20", "PD21", "PD22", "PD23";
|
|
|
- allwinner,function = "emac";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_40_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ uart1_rts_cts_pins: uart1_rts_cts_pins {
|
|
|
+ pins = "PG8", "PG9";
|
|
|
+ function = "uart1";
|
|
|
};
|
|
|
};
|
|
|
|
|
|
- ahb_rst: reset@1c202c0 {
|
|
|
- #reset-cells = <1>;
|
|
|
- compatible = "allwinner,sun6i-a31-clock-reset";
|
|
|
- reg = <0x01c202c0 0xc>;
|
|
|
- };
|
|
|
-
|
|
|
- apb1_rst: reset@1c202d0 {
|
|
|
- #reset-cells = <1>;
|
|
|
- compatible = "allwinner,sun6i-a31-clock-reset";
|
|
|
- reg = <0x01c202d0 0x4>;
|
|
|
- };
|
|
|
-
|
|
|
- apb2_rst: reset@1c202d8 {
|
|
|
- #reset-cells = <1>;
|
|
|
- compatible = "allwinner,sun6i-a31-clock-reset";
|
|
|
- reg = <0x01c202d8 0x4>;
|
|
|
- };
|
|
|
-
|
|
|
uart0: serial@1c28000 {
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
reg = <0x01c28000 0x400>;
|
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
reg-shift = <2>;
|
|
|
reg-io-width = <4>;
|
|
|
- clocks = <&bus_gates 112>;
|
|
|
- resets = <&apb2_rst 16>;
|
|
|
+ clocks = <&ccu 67>;
|
|
|
+ resets = <&ccu 46>;
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
@@ -562,8 +314,8 @@
|
|
|
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
reg-shift = <2>;
|
|
|
reg-io-width = <4>;
|
|
|
- clocks = <&bus_gates 113>;
|
|
|
- resets = <&apb2_rst 17>;
|
|
|
+ clocks = <&ccu 68>;
|
|
|
+ resets = <&ccu 47>;
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
@@ -573,8 +325,8 @@
|
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
reg-shift = <2>;
|
|
|
reg-io-width = <4>;
|
|
|
- clocks = <&bus_gates 114>;
|
|
|
- resets = <&apb2_rst 18>;
|
|
|
+ clocks = <&ccu 69>;
|
|
|
+ resets = <&ccu 48>;
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
@@ -584,8 +336,8 @@
|
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
reg-shift = <2>;
|
|
|
reg-io-width = <4>;
|
|
|
- clocks = <&bus_gates 115>;
|
|
|
- resets = <&apb2_rst 19>;
|
|
|
+ clocks = <&ccu 70>;
|
|
|
+ resets = <&ccu 49>;
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
@@ -595,24 +347,17 @@
|
|
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
reg-shift = <2>;
|
|
|
reg-io-width = <4>;
|
|
|
- clocks = <&bus_gates 116>;
|
|
|
- resets = <&apb2_rst 20>;
|
|
|
+ clocks = <&ccu 71>;
|
|
|
+ resets = <&ccu 50>;
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
|
- rtc: rtc@1f00000 {
|
|
|
- compatible = "allwinner,sun6i-a31-rtc";
|
|
|
- reg = <0x01f00000 0x54>;
|
|
|
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
- };
|
|
|
-
|
|
|
i2c0: i2c@1c2ac00 {
|
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
|
reg = <0x01c2ac00 0x400>;
|
|
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
- clocks = <&bus_gates 96>;
|
|
|
- resets = <&apb2_rst 0>;
|
|
|
+ clocks = <&ccu 63>;
|
|
|
+ resets = <&ccu 42>;
|
|
|
status = "disabled";
|
|
|
#address-cells = <1>;
|
|
|
#size-cells = <0>;
|
|
@@ -622,8 +367,8 @@
|
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
|
reg = <0x01c2b000 0x400>;
|
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
- clocks = <&bus_gates 97>;
|
|
|
- resets = <&apb2_rst 1>;
|
|
|
+ clocks = <&ccu 64>;
|
|
|
+ resets = <&ccu 43>;
|
|
|
status = "disabled";
|
|
|
#address-cells = <1>;
|
|
|
#size-cells = <0>;
|
|
@@ -633,54 +378,50 @@
|
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
|
reg = <0x01c2b400 0x400>;
|
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
- clocks = <&bus_gates 98>;
|
|
|
- resets = <&apb2_rst 2>;
|
|
|
+ clocks = <&ccu 65>;
|
|
|
+ resets = <&ccu 44>;
|
|
|
status = "disabled";
|
|
|
#address-cells = <1>;
|
|
|
#size-cells = <0>;
|
|
|
};
|
|
|
|
|
|
- emac: ethernet@01c30000 {
|
|
|
- compatible = "allwinner,sun50i-a64-emac";
|
|
|
- reg = <0x01c30000 0x2000>, <0x01c00030 0x4>;
|
|
|
- reg-names = "emac", "syscon";
|
|
|
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
- resets = <&ahb_rst 17>;
|
|
|
- reset-names = "ahb";
|
|
|
- clocks = <&bus_gates 17>;
|
|
|
- clock-names = "ahb";
|
|
|
- status = "disabled";
|
|
|
- #address-cells = <1>;
|
|
|
- #size-cells = <0>;
|
|
|
+ gic: interrupt-controller@1c81000 {
|
|
|
+ compatible = "arm,gic-400";
|
|
|
+ reg = <0x01c81000 0x1000>,
|
|
|
+ <0x01c82000 0x2000>,
|
|
|
+ <0x01c84000 0x2000>,
|
|
|
+ <0x01c86000 0x2000>;
|
|
|
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
|
+ interrupt-controller;
|
|
|
+ #interrupt-cells = <3>;
|
|
|
};
|
|
|
|
|
|
- usbphy: phy@1c1b810 {
|
|
|
- compatible = "allwinner,sun50i-a64-usb-phy",
|
|
|
- "allwinner,sun8i-a33-usb-phy";
|
|
|
- reg = <0x01c1b810 0x14>, <0x01c1b800 0x4>;
|
|
|
- reg-names = "phy_ctrl", "pmu1";
|
|
|
- status = "disabled";
|
|
|
- #phy-cells = <1>;
|
|
|
+ rtc: rtc@1f00000 {
|
|
|
+ compatible = "allwinner,sun6i-a31-rtc";
|
|
|
+ reg = <0x01f00000 0x54>;
|
|
|
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
};
|
|
|
|
|
|
- ehci1: usb@01c1b000 {
|
|
|
- compatible = "allwinner,sun50i-a64-ehci",
|
|
|
- "generic-ehci";
|
|
|
- reg = <0x01c1b000 0x100>;
|
|
|
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
- phys = <&usbphy 1>;
|
|
|
- phy-names = "usb";
|
|
|
- status = "disabled";
|
|
|
+ r_ccu: clock@1f01400 {
|
|
|
+ compatible = "allwinner,sun50i-a64-r-ccu";
|
|
|
+ reg = <0x01f01400 0x100>;
|
|
|
+ clocks = <&osc24M>, <&osc32k>, <&iosc>;
|
|
|
+ clock-names = "hosc", "losc", "iosc";
|
|
|
+ #clock-cells = <1>;
|
|
|
+ #reset-cells = <1>;
|
|
|
};
|
|
|
|
|
|
- ohci1: usb@01c1b400 {
|
|
|
- compatible = "allwinner,sun50i-a64-ohci",
|
|
|
- "generic-ohci";
|
|
|
- reg = <0x01c1b400 0x100>;
|
|
|
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
- phys = <&usbphy 1>;
|
|
|
- phy-names = "usb";
|
|
|
- status = "enabled";
|
|
|
+ r_pio: pinctrl@01f02c00 {
|
|
|
+ compatible = "allwinner,sun50i-a64-r-pinctrl";
|
|
|
+ reg = <0x01f02c00 0x400>;
|
|
|
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>;
|
|
|
+ clock-names = "apb", "hosc", "losc";
|
|
|
+ gpio-controller;
|
|
|
+ #gpio-cells = <3>;
|
|
|
+ interrupt-controller;
|
|
|
+ #interrupt-cells = <3>;
|
|
|
};
|
|
|
};
|
|
|
};
|