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@@ -340,6 +340,34 @@ config SYS_CACHELINE_SIZE
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default 64 if SYS_CACHE_SHIFT_6
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default 32 if SYS_CACHE_SHIFT_5
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+choice
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+ prompt "Select the ARM data write cache policy"
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+ default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
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+ TARGET_BCMNSP || CPU_PXA || RZA1
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+ default SYS_ARM_CACHE_WRITEBACK
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+
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+config SYS_ARM_CACHE_WRITEBACK
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+ bool "Write-back (WB)"
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+ help
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+ A write updates the cache only and marks the cache line as dirty.
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+ External memory is updated only when the line is evicted or explicitly
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+ cleaned.
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+
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+config SYS_ARM_CACHE_WRITETHROUGH
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+ bool "Write-through (WT)"
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+ help
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+ A write updates both the cache and the external memory system.
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+ This does not mark the cache line as dirty.
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+
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+config SYS_ARM_CACHE_WRITEALLOC
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+ bool "Write allocation (WA)"
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+ help
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+ A cache line is allocated on a write miss. This means that executing a
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+ store instruction on the processor might cause a burst read to occur.
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+ There is a linefill to obtain the data for the cache line, before the
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+ write is performed.
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+endchoice
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+
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config ARCH_CPU_INIT
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bool "Enable ARCH_CPU_INIT"
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help
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