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@@ -137,22 +137,79 @@ iomux_v3_cfg_t const usdhc3_pads[] = {
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int mx6_rgmii_rework(struct phy_device *phydev)
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{
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- /* control data pad skew - devaddr = 0x02, register = 0x04 */
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- ksz9031_phy_extended_write(phydev, 0x02,
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- MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
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- MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
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- /* rx data pad skew - devaddr = 0x02, register = 0x05 */
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- ksz9031_phy_extended_write(phydev, 0x02,
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- MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
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- MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
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- /* tx data pad skew - devaddr = 0x02, register = 0x05 */
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- ksz9031_phy_extended_write(phydev, 0x02,
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- MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
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- MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
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- /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
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- ksz9031_phy_extended_write(phydev, 0x02,
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- MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
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- MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
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+ int tmp;
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+
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+ switch (ksz9xx1_phy_get_id(phydev) & MII_KSZ9x31_SILICON_REV_MASK) {
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+ case PHY_ID_KSZ9131:
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+ /* read rxc dll control - devaddr = 0x02, register = 0x4c */
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+ tmp = ksz9031_phy_extended_read(phydev, 0x02,
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+ MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
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+ MII_KSZ9031_MOD_DATA_NO_POST_INC);
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+ /* disable rxdll bypass (enable 2ns skew delay on RXC) */
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+ tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
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+ /* rxc data pad skew 2ns - devaddr = 0x02, register = 0x4c */
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+ ksz9031_phy_extended_write(phydev, 0x02,
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+ MII_KSZ9131_EXT_RGMII_2NS_SKEW_RXDLL,
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+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
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+ tmp);
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+ /* read txc dll control - devaddr = 0x02, register = 0x4d */
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+ tmp = ksz9031_phy_extended_read(phydev, 0x02,
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+ MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
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+ MII_KSZ9031_MOD_DATA_NO_POST_INC);
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+ /* disable rxdll bypass (enable 2ns skew delay on TXC) */
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+ tmp &= ~MII_KSZ9131_RXTXDLL_BYPASS;
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+ /* txc data pad skew 2ns - devaddr = 0x02, register = 0x4d */
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+ ksz9031_phy_extended_write(phydev, 0x02,
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+ MII_KSZ9131_EXT_RGMII_2NS_SKEW_TXDLL,
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+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
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+ tmp);
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+
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+ /* control data pad skew - devaddr = 0x02, register = 0x04 */
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+ ksz9031_phy_extended_write(phydev, 0x02,
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+ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
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+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
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+ 0x007d);
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+ /* rx data pad skew - devaddr = 0x02, register = 0x05 */
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+ ksz9031_phy_extended_write(phydev, 0x02,
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+ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
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+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
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+ 0x7777);
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+ /* tx data pad skew - devaddr = 0x02, register = 0x05 */
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+ ksz9031_phy_extended_write(phydev, 0x02,
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+ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
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+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
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+ 0xdddd);
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+ /* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
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+ ksz9031_phy_extended_write(phydev, 0x02,
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+ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
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+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
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+ 0x0007);
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+ break;
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+ case PHY_ID_KSZ9031:
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+ default:
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+ /* control data pad skew - devaddr = 0x02, register = 0x04 */
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+ ksz9031_phy_extended_write(phydev, 0x02,
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+ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
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+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
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+ 0x0000);
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+ /* rx data pad skew - devaddr = 0x02, register = 0x05 */
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+ ksz9031_phy_extended_write(phydev, 0x02,
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+ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
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+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
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+ 0x0000);
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+ /* tx data pad skew - devaddr = 0x02, register = 0x05 */
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+ ksz9031_phy_extended_write(phydev, 0x02,
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+ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
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+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
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+ 0x0000);
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+ /* gtx and rx clock pad skew - devaddr = 0x02,register = 0x08 */
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+ ksz9031_phy_extended_write(phydev, 0x02,
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+ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
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+ MII_KSZ9031_MOD_DATA_NO_POST_INC,
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+ 0x03FF);
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+ break;
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+ }
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+
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return 0;
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}
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