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@@ -154,16 +154,12 @@ __secondary_start_page:
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ori r3,r3,toreset(__spin_table_addr)@l
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lwz r3,0(r3)
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- /*
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- * r10 has the base address for the entry.
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- * we cannot access it yet before setting up a new TLB
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- */
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mfspr r0,SPRN_PIR
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#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
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/*
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* PIR definition for Chassis 2
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* 0-17 Reserved (logic 0s)
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- * 8-19 CHIP_ID, 2'b00 - SoC 1
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+ * 18-19 CHIP_ID, 2'b00 - SoC 1
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* all others - reserved
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* 20-24 CLUSTER_ID 5'b00000 - CCM 1
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* all others - reserved
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@@ -177,32 +173,33 @@ __secondary_start_page:
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* 2'b11 - core 3
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* 29-31 THREAD_ID 3'b000 - thread 0
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* 3'b001 - thread 1
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+ *
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+ * Power-on PIR increments threads by 0x01, cores within a cluster by 0x08
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+ * and clusters by 0x20.
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+ *
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+ * We renumber PIR so that all threads in the system are consecutive.
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*/
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- rlwinm r4,r0,29,25,31
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+
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+ rlwinm r8,r0,29,0x03 /* r8 = core within cluster */
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+ srwi r10,r0,5 /* r10 = cluster */
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+
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+ mulli r5,r10,CONFIG_SYS_FSL_CORES_PER_CLUSTER
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+ add r5,r5,r8 /* for spin table index */
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+ mulli r4,r5,CONFIG_SYS_FSL_THREADS_PER_CORE /* for PIR */
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#elif defined(CONFIG_E500MC)
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rlwinm r4,r0,27,27,31
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+ mr r5,r4
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#else
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mr r4,r0
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+ mr r5,r4
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#endif
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- slwi r8,r4,6 /* spin table is padded to 64 byte */
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- add r10,r3,r8
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-#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
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- mfspr r0,SPRN_PIR
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/*
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- * core 0 thread 0: pir reset value 0x00, new pir 0
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- * core 0 thread 1: pir reset value 0x01, new pir 1
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- * core 1 thread 0: pir reset value 0x08, new pir 2
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- * core 1 thread 1: pir reset value 0x09, new pir 3
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- * core 2 thread 0: pir reset value 0x10, new pir 4
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- * core 2 thread 1: pir reset value 0x11, new pir 5
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- * etc.
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- *
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- * Only thread 0 of each core will be running, updating PIR doesn't
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- * need to deal with the thread bits.
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+ * r10 has the base address for the entry.
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+ * we cannot access it yet before setting up a new TLB
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*/
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- rlwinm r4,r0,30,24,30
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-#endif
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+ slwi r8,r5,6 /* spin table is padded to 64 byte */
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+ add r10,r3,r8
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mtspr SPRN_PIR,r4 /* write to PIR register */
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