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@@ -2,6 +2,7 @@
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* Copyright (C) 2015 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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* Copyright (c) 2016, NVIDIA CORPORATION.
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+ * Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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@@ -10,6 +11,7 @@
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#include <clk.h>
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#include <clk-uclass.h>
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#include <dm.h>
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+#include <dm/read.h>
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#include <dt-structs.h>
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#include <errno.h>
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@@ -101,6 +103,122 @@ int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
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{
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return clk_get_by_indexed_prop(dev, "clocks", index, clk);
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}
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+
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+static int clk_set_default_parents(struct udevice *dev)
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+{
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+ struct clk clk, parent_clk;
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+ int index;
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+ int num_parents;
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+ int ret;
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+
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+ num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
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+ "#clock-cells");
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+ if (num_parents < 0) {
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+ debug("%s: could not read assigned-clock-parents for %p\n",
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+ __func__, dev);
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+ return 0;
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+ }
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+
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+ for (index = 0; index < num_parents; index++) {
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+ ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
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+ index, &parent_clk);
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+ if (ret) {
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+ debug("%s: could not get parent clock %d for %s\n",
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+ __func__, index, dev_read_name(dev));
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+ return ret;
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+ }
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+
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+ ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
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+ index, &clk);
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+ if (ret) {
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+ debug("%s: could not get assigned clock %d for %s\n",
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+ __func__, index, dev_read_name(dev));
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+ return ret;
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+ }
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+
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+ ret = clk_set_parent(&clk, &parent_clk);
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+
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+ /*
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+ * Not all drivers may support clock-reparenting (as of now).
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+ * Ignore errors due to this.
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+ */
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+ if (ret == -ENOSYS)
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+ continue;
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+
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+ if (ret) {
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+ debug("%s: failed to reparent clock %d for %s\n",
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+ __func__, index, dev_read_name(dev));
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+ return ret;
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+ }
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+ }
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+
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+ return 0;
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+}
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+
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+static int clk_set_default_rates(struct udevice *dev)
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+{
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+ struct clk clk;
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+ int index;
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+ int num_rates;
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+ int size;
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+ int ret = 0;
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+ u32 *rates = NULL;
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+
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+ size = dev_read_size(dev, "assigned-clock-rates");
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+ if (size < 0)
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+ return 0;
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+
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+ num_rates = size / sizeof(u32);
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+ rates = calloc(num_rates, sizeof(u32));
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+ if (!rates)
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+ return -ENOMEM;
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+
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+ ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates);
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+ if (ret)
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+ goto fail;
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+
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+ for (index = 0; index < num_rates; index++) {
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+ ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
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+ index, &clk);
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+ if (ret) {
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+ debug("%s: could not get assigned clock %d for %s\n",
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+ __func__, index, dev_read_name(dev));
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+ continue;
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+ }
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+
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+ ret = clk_set_rate(&clk, rates[index]);
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+ if (ret < 0) {
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+ debug("%s: failed to set rate on clock %d for %s\n",
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+ __func__, index, dev_read_name(dev));
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+ break;
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+ }
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+ }
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+
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+fail:
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+ free(rates);
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+ return ret;
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+}
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+
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+int clk_set_defaults(struct udevice *dev)
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+{
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+ int ret;
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+
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+ /* If this is running pre-reloc state, don't take any action. */
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+ if (!(gd->flags & GD_FLG_RELOC))
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+ return 0;
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+
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+ debug("%s(%s)\n", __func__, dev_read_name(dev));
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+
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+ ret = clk_set_default_parents(dev);
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+ if (ret)
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+ return ret;
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+
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+ ret = clk_set_default_rates(dev);
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+ if (ret < 0)
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+ return ret;
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+
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+ return 0;
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+}
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# endif /* OF_PLATDATA */
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int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
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