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@@ -1,14 +1,18 @@
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#include <dt-bindings/clock/tegra124-car.h>
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#include <dt-bindings/gpio/tegra-gpio.h>
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+#include <dt-bindings/memory/tegra124-mc.h>
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#include <dt-bindings/pinctrl/pinctrl-tegra.h>
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-#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/reset/tegra124-car.h>
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+#include <dt-bindings/thermal/tegra124-soctherm.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "nvidia,tegra124";
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- interrupt-parent = <&gic>;
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+ interrupt-parent = <&lic>;
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+
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pcie-controller@01003000 {
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compatible = "nvidia,tegra124-pcie";
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@@ -100,6 +104,8 @@
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resets = <&tegra_car 27>;
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reset-names = "dc";
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+ iommus = <&mc TEGRA_SWGROUP_DC>;
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+
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nvidia,head = <0>;
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};
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@@ -113,6 +119,8 @@
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resets = <&tegra_car 26>;
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reset-names = "dc";
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+ iommus = <&mc TEGRA_SWGROUP_DCB>;
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+
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nvidia,head = <1>;
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};
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@@ -165,49 +173,68 @@
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<0x50046000 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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+ interrupt-parent = <&gic>;
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+ };
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+
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+ gpu@57000000 {
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+ compatible = "nvidia,gk20a";
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+ reg = <0x57000000 0x01000000>,
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+ <0x58000000 0x01000000>;
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+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "stall", "nonstall";
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+ clocks = <&tegra_car TEGRA124_CLK_GPU>,
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+ <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
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+ clock-names = "gpu", "pwr";
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+ resets = <&tegra_car 184>;
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+ reset-names = "gpu";
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+
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+ iommus = <&mc TEGRA_SWGROUP_GPU>;
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+
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+ status = "disabled";
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+ };
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+
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+ lic: interrupt-controller@60004000 {
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+ compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
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+ interrupt-controller;
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+ #interrupt-cells = <3>;
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+ interrupt-parent = <&gic>;
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+ };
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+
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+ timer@60005000 {
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+ compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
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+ reg = <0x60005000 0x400>;
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+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&tegra_car TEGRA124_CLK_TIMER>;
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};
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tegra_car: clock@60006000 {
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compatible = "nvidia,tegra124-car";
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reg = <0x60006000 0x1000>;
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#clock-cells = <1>;
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+ #reset-cells = <1>;
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+ nvidia,external-memory-controller = <&emc>;
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};
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- apbdma: dma@60020000 {
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- compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
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- reg = <0x60020000 0x1400>;
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- interrupts = <0 104 0x04
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- 0 105 0x04
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- 0 106 0x04
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- 0 107 0x04
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- 0 108 0x04
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- 0 109 0x04
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- 0 110 0x04
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- 0 111 0x04
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- 0 112 0x04
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- 0 113 0x04
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- 0 114 0x04
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- 0 115 0x04
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- 0 116 0x04
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- 0 117 0x04
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- 0 118 0x04
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- 0 119 0x04
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- 0 128 0x04
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- 0 129 0x04
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- 0 130 0x04
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- 0 131 0x04
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- 0 132 0x04
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- 0 133 0x04
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- 0 134 0x04
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- 0 135 0x04
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- 0 136 0x04
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- 0 137 0x04
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- 0 138 0x04
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- 0 139 0x04
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- 0 140 0x04
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- 0 141 0x04
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- 0 142 0x04
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- 0 143 0x04>;
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+ flow-controller@60007000 {
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+ compatible = "nvidia,tegra124-flowctrl";
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+ reg = <0x60007000 0x1000>;
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+ };
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+
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+ actmon@6000c800 {
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+ compatible = "nvidia,tegra124-actmon";
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+ reg = <0x6000c800 0x400>;
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+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
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+ <&tegra_car TEGRA124_CLK_EMC>;
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+ clock-names = "actmon", "emc";
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+ resets = <&tegra_car 119>;
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+ reset-names = "actmon";
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};
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gpio: gpio@6000d000 {
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@@ -225,68 +252,73 @@
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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+ /*
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+ gpio-ranges = <&pinmux 0 0 251>;
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+ */
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};
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- i2c@7000c000 {
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- compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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- reg = <0x7000c000 0x100>;
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- interrupts = <0 38 0x04>;
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- #address-cells = <1>;
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- #size-cells = <0>;
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- clocks = <&tegra_car 12>;
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- status = "disabled";
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- };
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-
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- i2c@7000c400 {
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- compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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- reg = <0x7000c400 0x100>;
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- interrupts = <0 84 0x04>;
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- #address-cells = <1>;
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- #size-cells = <0>;
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- clocks = <&tegra_car 54>;
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- status = "disabled";
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- };
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-
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- i2c@7000c500 {
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- compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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- reg = <0x7000c500 0x100>;
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- interrupts = <0 92 0x04>;
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- #address-cells = <1>;
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- #size-cells = <0>;
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- clocks = <&tegra_car 67>;
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- status = "disabled";
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- };
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-
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- i2c@7000c700 {
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- compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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- reg = <0x7000c700 0x100>;
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- interrupts = <0 120 0x04>;
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- #address-cells = <1>;
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- #size-cells = <0>;
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- clocks = <&tegra_car 103>;
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- status = "disabled";
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+ apbdma: dma@60020000 {
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+ compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
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+ reg = <0x60020000 0x1400>;
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+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
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+ resets = <&tegra_car 34>;
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+ reset-names = "dma";
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+ #dma-cells = <1>;
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};
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- i2c@7000d000 {
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- compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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- reg = <0x7000d000 0x100>;
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- interrupts = <0 53 0x04>;
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- #address-cells = <1>;
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- #size-cells = <0>;
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- clocks = <&tegra_car 47>;
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- status = "disabled";
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+ apbmisc@70000800 {
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+ compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
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+ reg = <0x70000800 0x64>, /* Chip revision */
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+ <0x7000e864 0x04>; /* Strapping options */
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};
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- i2c@7000d100 {
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- compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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- reg = <0x7000d100 0x100>;
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- interrupts = <0 53 0x04>;
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- #address-cells = <1>;
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- #size-cells = <0>;
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- clocks = <&tegra_car 47>;
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- status = "disabled";
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+ pinmux: pinmux@70000868 {
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+ compatible = "nvidia,tegra124-pinmux";
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+ reg = <0x70000868 0x164>, /* Pad control registers */
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+ <0x70003000 0x434>, /* Mux registers */
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+ <0x70000820 0x008>; /* MIPI pad control */
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};
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+ /*
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+ * There are two serial driver i.e. 8250 based simple serial
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+ * driver and APB DMA based serial driver for higher baudrate
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+ * and performace. To enable the 8250 based driver, the compatible
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+ * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
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+ * the APB DMA based serial driver, the comptible is
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+ * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
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+ */
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uarta: serial@70006000 {
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compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
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reg = <0x70006000 0x40>;
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@@ -339,19 +371,6 @@
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status = "disabled";
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};
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- uarte: serial@70006400 {
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- compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
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- reg = <0x70006400 0x40>;
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- reg-shift = <2>;
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- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&tegra_car TEGRA124_CLK_UARTE>;
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- resets = <&tegra_car 66>;
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- reset-names = "serial";
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- dmas = <&apbdma 20>, <&apbdma 20>;
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- dma-names = "rx", "tx";
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- status = "disabled";
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- };
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-
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pwm: pwm@7000a000 {
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compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
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reg = <0x7000a000 0x100>;
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@@ -362,75 +381,254 @@
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status = "disabled";
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};
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+ i2c@7000c000 {
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+ compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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+ reg = <0x7000c000 0x100>;
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+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ clocks = <&tegra_car TEGRA124_CLK_I2C1>;
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+ clock-names = "div-clk";
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+ resets = <&tegra_car 12>;
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+ reset-names = "i2c";
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+ dmas = <&apbdma 21>, <&apbdma 21>;
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+ dma-names = "rx", "tx";
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+ status = "disabled";
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+ };
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+
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+ i2c@7000c400 {
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+ compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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+ reg = <0x7000c400 0x100>;
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+ interrupts = <0 84 0x04>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ clocks = <&tegra_car 54>;
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+ status = "disabled";
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+ };
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+
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+ i2c@7000c500 {
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+ compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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+ reg = <0x7000c500 0x100>;
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+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ clocks = <&tegra_car TEGRA124_CLK_I2C3>;
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+ clock-names = "div-clk";
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+ resets = <&tegra_car 67>;
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+ reset-names = "i2c";
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+ dmas = <&apbdma 23>, <&apbdma 23>;
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+ dma-names = "rx", "tx";
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+ status = "disabled";
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+ };
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+
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+ i2c@7000c700 {
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+ compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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+ reg = <0x7000c700 0x100>;
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+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ clocks = <&tegra_car TEGRA124_CLK_I2C4>;
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+ clock-names = "div-clk";
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+ resets = <&tegra_car 103>;
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+ reset-names = "i2c";
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+ dmas = <&apbdma 26>, <&apbdma 26>;
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+ dma-names = "rx", "tx";
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+ status = "disabled";
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+ };
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+
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+ i2c@7000d000 {
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+ compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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+ reg = <0x7000d000 0x100>;
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+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ clocks = <&tegra_car TEGRA124_CLK_I2C5>;
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+ clock-names = "div-clk";
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+ resets = <&tegra_car 47>;
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+ reset-names = "i2c";
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+ dmas = <&apbdma 24>, <&apbdma 24>;
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+ dma-names = "rx", "tx";
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+ status = "disabled";
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+ };
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+
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+ i2c@7000d100 {
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+ compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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+ reg = <0x7000d100 0x100>;
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+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ clocks = <&tegra_car TEGRA124_CLK_I2C6>;
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+ clock-names = "div-clk";
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+ resets = <&tegra_car 166>;
|
|
|
+ reset-names = "i2c";
|
|
|
+ dmas = <&apbdma 30>, <&apbdma 30>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
spi@7000d400 {
|
|
|
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
|
|
reg = <0x7000d400 0x200>;
|
|
|
- interrupts = <0 59 0x04>;
|
|
|
- nvidia,dma-request-selector = <&apbdma 15>;
|
|
|
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
#address-cells = <1>;
|
|
|
#size-cells = <0>;
|
|
|
+ clocks = <&tegra_car TEGRA124_CLK_SBC1>;
|
|
|
+ clock-names = "spi";
|
|
|
+ resets = <&tegra_car 41>;
|
|
|
+ reset-names = "spi";
|
|
|
+ dmas = <&apbdma 15>, <&apbdma 15>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
status = "disabled";
|
|
|
- clocks = <&tegra_car 41>;
|
|
|
};
|
|
|
|
|
|
spi@7000d600 {
|
|
|
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
|
|
reg = <0x7000d600 0x200>;
|
|
|
- interrupts = <0 82 0x04>;
|
|
|
- nvidia,dma-request-selector = <&apbdma 16>;
|
|
|
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
#address-cells = <1>;
|
|
|
#size-cells = <0>;
|
|
|
+ clocks = <&tegra_car TEGRA124_CLK_SBC2>;
|
|
|
+ clock-names = "spi";
|
|
|
+ resets = <&tegra_car 44>;
|
|
|
+ reset-names = "spi";
|
|
|
+ dmas = <&apbdma 16>, <&apbdma 16>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
status = "disabled";
|
|
|
- clocks = <&tegra_car 44>;
|
|
|
};
|
|
|
|
|
|
spi@7000d800 {
|
|
|
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
|
|
reg = <0x7000d800 0x200>;
|
|
|
- interrupts = <0 83 0x04>;
|
|
|
- nvidia,dma-request-selector = <&apbdma 17>;
|
|
|
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
#address-cells = <1>;
|
|
|
#size-cells = <0>;
|
|
|
+ clocks = <&tegra_car TEGRA124_CLK_SBC3>;
|
|
|
+ clock-names = "spi";
|
|
|
+ resets = <&tegra_car 46>;
|
|
|
+ reset-names = "spi";
|
|
|
+ dmas = <&apbdma 17>, <&apbdma 17>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
status = "disabled";
|
|
|
- clocks = <&tegra_car 46>;
|
|
|
};
|
|
|
|
|
|
spi@7000da00 {
|
|
|
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
|
|
reg = <0x7000da00 0x200>;
|
|
|
- interrupts = <0 93 0x04>;
|
|
|
- nvidia,dma-request-selector = <&apbdma 18>;
|
|
|
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
#address-cells = <1>;
|
|
|
#size-cells = <0>;
|
|
|
+ clocks = <&tegra_car TEGRA124_CLK_SBC4>;
|
|
|
+ clock-names = "spi";
|
|
|
+ resets = <&tegra_car 68>;
|
|
|
+ reset-names = "spi";
|
|
|
+ dmas = <&apbdma 18>, <&apbdma 18>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
status = "disabled";
|
|
|
- clocks = <&tegra_car 68>;
|
|
|
};
|
|
|
|
|
|
spi@7000dc00 {
|
|
|
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
|
|
reg = <0x7000dc00 0x200>;
|
|
|
- interrupts = <0 94 0x04>;
|
|
|
- nvidia,dma-request-selector = <&apbdma 27>;
|
|
|
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
#address-cells = <1>;
|
|
|
#size-cells = <0>;
|
|
|
+ clocks = <&tegra_car TEGRA124_CLK_SBC5>;
|
|
|
+ clock-names = "spi";
|
|
|
+ resets = <&tegra_car 104>;
|
|
|
+ reset-names = "spi";
|
|
|
+ dmas = <&apbdma 27>, <&apbdma 27>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
status = "disabled";
|
|
|
- clocks = <&tegra_car 104>;
|
|
|
};
|
|
|
|
|
|
spi@7000de00 {
|
|
|
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
|
|
reg = <0x7000de00 0x200>;
|
|
|
- interrupts = <0 79 0x04>;
|
|
|
- nvidia,dma-request-selector = <&apbdma 28>;
|
|
|
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
#address-cells = <1>;
|
|
|
#size-cells = <0>;
|
|
|
+ clocks = <&tegra_car TEGRA124_CLK_SBC6>;
|
|
|
+ clock-names = "spi";
|
|
|
+ resets = <&tegra_car 105>;
|
|
|
+ reset-names = "spi";
|
|
|
+ dmas = <&apbdma 28>, <&apbdma 28>;
|
|
|
+ dma-names = "rx", "tx";
|
|
|
status = "disabled";
|
|
|
- clocks = <&tegra_car 105>;
|
|
|
+ };
|
|
|
+
|
|
|
+ rtc@7000e000 {
|
|
|
+ compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
|
|
|
+ reg = <0x7000e000 0x100>;
|
|
|
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&tegra_car TEGRA124_CLK_RTC>;
|
|
|
};
|
|
|
|
|
|
pmc@7000e400 {
|
|
|
compatible = "nvidia,tegra124-pmc";
|
|
|
reg = <0x7000e400 0x400>;
|
|
|
+ clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
|
|
|
+ clock-names = "pclk", "clk32k_in";
|
|
|
+ };
|
|
|
+
|
|
|
+ fuse@7000f800 {
|
|
|
+ compatible = "nvidia,tegra124-efuse";
|
|
|
+ reg = <0x7000f800 0x400>;
|
|
|
+ clocks = <&tegra_car TEGRA124_CLK_FUSE>;
|
|
|
+ clock-names = "fuse";
|
|
|
+ resets = <&tegra_car 39>;
|
|
|
+ reset-names = "fuse";
|
|
|
+ };
|
|
|
+
|
|
|
+ mc: memory-controller@70019000 {
|
|
|
+ compatible = "nvidia,tegra124-mc";
|
|
|
+ reg = <0x70019000 0x1000>;
|
|
|
+ clocks = <&tegra_car TEGRA124_CLK_MC>;
|
|
|
+ clock-names = "mc";
|
|
|
+
|
|
|
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+
|
|
|
+ #iommu-cells = <1>;
|
|
|
+ };
|
|
|
+
|
|
|
+ emc: emc@7001b000 {
|
|
|
+ compatible = "nvidia,tegra124-emc";
|
|
|
+ reg = <0x7001b000 0x1000>;
|
|
|
+
|
|
|
+ nvidia,memory-controller = <&mc>;
|
|
|
+ };
|
|
|
+
|
|
|
+ sata@70020000 {
|
|
|
+ compatible = "nvidia,tegra124-ahci";
|
|
|
+ reg = <0x70027000 0x2000>, /* AHCI */
|
|
|
+ <0x70020000 0x7000>; /* SATA */
|
|
|
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&tegra_car TEGRA124_CLK_SATA>,
|
|
|
+ <&tegra_car TEGRA124_CLK_SATA_OOB>,
|
|
|
+ <&tegra_car TEGRA124_CLK_CML1>,
|
|
|
+ <&tegra_car TEGRA124_CLK_PLL_E>;
|
|
|
+ clock-names = "sata", "sata-oob", "cml1", "pll_e";
|
|
|
+ resets = <&tegra_car 124>,
|
|
|
+ <&tegra_car 123>,
|
|
|
+ <&tegra_car 129>;
|
|
|
+ reset-names = "sata", "sata-oob", "sata-cold";
|
|
|
+ phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
|
|
|
+ phy-names = "sata-phy";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ hda@70030000 {
|
|
|
+ compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
|
|
|
+ reg = <0x70030000 0x10000>;
|
|
|
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&tegra_car TEGRA124_CLK_HDA>,
|
|
|
+ <&tegra_car TEGRA124_CLK_HDA2HDMI>,
|
|
|
+ <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
|
|
|
+ clock-names = "hda", "hda2hdmi", "hda2codec_2x";
|
|
|
+ resets = <&tegra_car 125>, /* hda */
|
|
|
+ <&tegra_car 128>, /* hda2hdmi */
|
|
|
+ <&tegra_car 111>; /* hda2codec_2x */
|
|
|
+ reset-names = "hda", "hda2hdmi", "hda2codec_2x";
|
|
|
+ status = "disabled";
|
|
|
};
|
|
|
|
|
|
padctl: padctl@7009f000 {
|
|
@@ -445,32 +643,76 @@
|
|
|
sdhci@700b0000 {
|
|
|
compatible = "nvidia,tegra124-sdhci";
|
|
|
reg = <0x700b0000 0x200>;
|
|
|
- interrupts = <0 14 0x04>;
|
|
|
- clocks = <&tegra_car 14>;
|
|
|
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
|
|
|
+ resets = <&tegra_car 14>;
|
|
|
+ reset-names = "sdhci";
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
|
sdhci@700b0200 {
|
|
|
compatible = "nvidia,tegra124-sdhci";
|
|
|
reg = <0x700b0200 0x200>;
|
|
|
- interrupts = <0 15 0x04>;
|
|
|
- clocks = <&tegra_car 9>;
|
|
|
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
|
|
|
+ resets = <&tegra_car 9>;
|
|
|
+ reset-names = "sdhci";
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
|
sdhci@700b0400 {
|
|
|
compatible = "nvidia,tegra124-sdhci";
|
|
|
reg = <0x700b0400 0x200>;
|
|
|
- interrupts = <0 19 0x04>;
|
|
|
- clocks = <&tegra_car 69>;
|
|
|
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
|
|
|
+ resets = <&tegra_car 69>;
|
|
|
+ reset-names = "sdhci";
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
|
sdhci@700b0600 {
|
|
|
compatible = "nvidia,tegra124-sdhci";
|
|
|
reg = <0x700b0600 0x200>;
|
|
|
- interrupts = <0 31 0x04>;
|
|
|
- clocks = <&tegra_car 15>;
|
|
|
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
|
|
|
+ resets = <&tegra_car 15>;
|
|
|
+ reset-names = "sdhci";
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ soctherm: thermal-sensor@700e2000 {
|
|
|
+ compatible = "nvidia,tegra124-soctherm";
|
|
|
+ reg = <0x700e2000 0x1000>;
|
|
|
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
|
|
|
+ <&tegra_car TEGRA124_CLK_SOC_THERM>;
|
|
|
+ clock-names = "tsensor", "soctherm";
|
|
|
+ resets = <&tegra_car 78>;
|
|
|
+ reset-names = "soctherm";
|
|
|
+ #thermal-sensor-cells = <1>;
|
|
|
+ };
|
|
|
+
|
|
|
+ dfll: clock@70110000 {
|
|
|
+ compatible = "nvidia,tegra124-dfll";
|
|
|
+ reg = <0x70110000 0x100>, /* DFLL control */
|
|
|
+ <0x70110000 0x100>, /* I2C output control */
|
|
|
+ <0x70110100 0x100>, /* Integrated I2C controller */
|
|
|
+ <0x70110200 0x100>; /* Look-up table RAM */
|
|
|
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
|
|
|
+ <&tegra_car TEGRA124_CLK_DFLL_REF>,
|
|
|
+ <&tegra_car TEGRA124_CLK_I2C5>;
|
|
|
+ clock-names = "soc", "ref", "i2c";
|
|
|
+ resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
|
|
|
+ reset-names = "dvco";
|
|
|
+ #clock-cells = <0>;
|
|
|
+ clock-output-names = "dfllCPU_out";
|
|
|
+ nvidia,sample-rate = <12500>;
|
|
|
+ nvidia,droop-ctrl = <0x00000f00>;
|
|
|
+ nvidia,force-mode = <1>;
|
|
|
+ nvidia,cf = <10>;
|
|
|
+ nvidia,ci = <0>;
|
|
|
+ nvidia,cg = <2>;
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
@@ -580,27 +822,206 @@
|
|
|
usb@7d000000 {
|
|
|
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
|
|
|
reg = <0x7d000000 0x4000>;
|
|
|
- interrupts = < 52 >;
|
|
|
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ phy_type = "utmi";
|
|
|
+ clocks = <&tegra_car TEGRA124_CLK_USBD>;
|
|
|
+ resets = <&tegra_car 22>;
|
|
|
+ reset-names = "usb";
|
|
|
+ nvidia,phy = <&phy1>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ phy1: usb-phy@7d000000 {
|
|
|
+ compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
|
|
|
+ reg = <0x7d000000 0x4000>,
|
|
|
+ <0x7d000000 0x4000>;
|
|
|
phy_type = "utmi";
|
|
|
- clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
|
|
|
+ clocks = <&tegra_car TEGRA124_CLK_USBD>,
|
|
|
+ <&tegra_car TEGRA124_CLK_PLL_U>,
|
|
|
+ <&tegra_car TEGRA124_CLK_USBD>;
|
|
|
+ clock-names = "reg", "pll_u", "utmi-pads";
|
|
|
+ resets = <&tegra_car 22>, <&tegra_car 22>;
|
|
|
+ reset-names = "usb", "utmi-pads";
|
|
|
+ nvidia,hssync-start-delay = <0>;
|
|
|
+ nvidia,idle-wait-delay = <17>;
|
|
|
+ nvidia,elastic-limit = <16>;
|
|
|
+ nvidia,term-range-adj = <6>;
|
|
|
+ nvidia,xcvr-setup = <9>;
|
|
|
+ nvidia,xcvr-lsfslew = <0>;
|
|
|
+ nvidia,xcvr-lsrslew = <3>;
|
|
|
+ nvidia,hssquelch-level = <2>;
|
|
|
+ nvidia,hsdiscon-level = <5>;
|
|
|
+ nvidia,xcvr-hsslew = <12>;
|
|
|
+ nvidia,has-utmi-pad-registers;
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
|
usb@7d004000 {
|
|
|
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
|
|
|
reg = <0x7d004000 0x4000>;
|
|
|
- interrupts = < 53 >;
|
|
|
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
phy_type = "hsic";
|
|
|
- clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
|
|
|
+ clocks = <&tegra_car TEGRA124_CLK_USB2>;
|
|
|
+ resets = <&tegra_car 58>;
|
|
|
+ reset-names = "usb";
|
|
|
+ nvidia,phy = <&phy2>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ phy2: usb-phy@7d004000 {
|
|
|
+ compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
|
|
|
+ reg = <0x7d004000 0x4000>,
|
|
|
+ <0x7d000000 0x4000>;
|
|
|
+ phy_type = "utmi";
|
|
|
+ clocks = <&tegra_car TEGRA124_CLK_USB2>,
|
|
|
+ <&tegra_car TEGRA124_CLK_PLL_U>,
|
|
|
+ <&tegra_car TEGRA124_CLK_USBD>;
|
|
|
+ clock-names = "reg", "pll_u", "utmi-pads";
|
|
|
+ resets = <&tegra_car 58>, <&tegra_car 22>;
|
|
|
+ reset-names = "usb", "utmi-pads";
|
|
|
+ nvidia,hssync-start-delay = <0>;
|
|
|
+ nvidia,idle-wait-delay = <17>;
|
|
|
+ nvidia,elastic-limit = <16>;
|
|
|
+ nvidia,term-range-adj = <6>;
|
|
|
+ nvidia,xcvr-setup = <9>;
|
|
|
+ nvidia,xcvr-lsfslew = <0>;
|
|
|
+ nvidia,xcvr-lsrslew = <3>;
|
|
|
+ nvidia,hssquelch-level = <2>;
|
|
|
+ nvidia,hsdiscon-level = <5>;
|
|
|
+ nvidia,xcvr-hsslew = <12>;
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
|
usb@7d008000 {
|
|
|
compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
|
|
|
reg = <0x7d008000 0x4000>;
|
|
|
- interrupts = < 129 >;
|
|
|
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ phy_type = "utmi";
|
|
|
+ clocks = <&tegra_car TEGRA124_CLK_USB3>;
|
|
|
+ resets = <&tegra_car 59>;
|
|
|
+ reset-names = "usb";
|
|
|
+ nvidia,phy = <&phy3>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ phy3: usb-phy@7d008000 {
|
|
|
+ compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
|
|
|
+ reg = <0x7d008000 0x4000>,
|
|
|
+ <0x7d000000 0x4000>;
|
|
|
phy_type = "utmi";
|
|
|
- clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
|
|
|
+ clocks = <&tegra_car TEGRA124_CLK_USB3>,
|
|
|
+ <&tegra_car TEGRA124_CLK_PLL_U>,
|
|
|
+ <&tegra_car TEGRA124_CLK_USBD>;
|
|
|
+ clock-names = "reg", "pll_u", "utmi-pads";
|
|
|
+ resets = <&tegra_car 59>, <&tegra_car 22>;
|
|
|
+ reset-names = "usb", "utmi-pads";
|
|
|
+ nvidia,hssync-start-delay = <0>;
|
|
|
+ nvidia,idle-wait-delay = <17>;
|
|
|
+ nvidia,elastic-limit = <16>;
|
|
|
+ nvidia,term-range-adj = <6>;
|
|
|
+ nvidia,xcvr-setup = <9>;
|
|
|
+ nvidia,xcvr-lsfslew = <0>;
|
|
|
+ nvidia,xcvr-lsrslew = <3>;
|
|
|
+ nvidia,hssquelch-level = <2>;
|
|
|
+ nvidia,hsdiscon-level = <5>;
|
|
|
+ nvidia,xcvr-hsslew = <12>;
|
|
|
status = "disabled";
|
|
|
};
|
|
|
+
|
|
|
+ cpus {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+
|
|
|
+ cpu@0 {
|
|
|
+ device_type = "cpu";
|
|
|
+ compatible = "arm,cortex-a15";
|
|
|
+ reg = <0>;
|
|
|
+
|
|
|
+ clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
|
|
|
+ <&tegra_car TEGRA124_CLK_CCLK_LP>,
|
|
|
+ <&tegra_car TEGRA124_CLK_PLL_X>,
|
|
|
+ <&tegra_car TEGRA124_CLK_PLL_P>,
|
|
|
+ <&dfll>;
|
|
|
+ clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
|
|
|
+ /* FIXME: what's the actual transition time? */
|
|
|
+ clock-latency = <300000>;
|
|
|
+ };
|
|
|
+
|
|
|
+ cpu@1 {
|
|
|
+ device_type = "cpu";
|
|
|
+ compatible = "arm,cortex-a15";
|
|
|
+ reg = <1>;
|
|
|
+ };
|
|
|
+
|
|
|
+ cpu@2 {
|
|
|
+ device_type = "cpu";
|
|
|
+ compatible = "arm,cortex-a15";
|
|
|
+ reg = <2>;
|
|
|
+ };
|
|
|
+
|
|
|
+ cpu@3 {
|
|
|
+ device_type = "cpu";
|
|
|
+ compatible = "arm,cortex-a15";
|
|
|
+ reg = <3>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ pmu {
|
|
|
+ compatible = "arm,cortex-a15-pmu";
|
|
|
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ interrupt-affinity = <&{/cpus/cpu@0}>,
|
|
|
+ <&{/cpus/cpu@1}>,
|
|
|
+ <&{/cpus/cpu@2}>,
|
|
|
+ <&{/cpus/cpu@3}>;
|
|
|
+ };
|
|
|
+
|
|
|
+ thermal-zones {
|
|
|
+ cpu {
|
|
|
+ polling-delay-passive = <1000>;
|
|
|
+ polling-delay = <1000>;
|
|
|
+
|
|
|
+ thermal-sensors =
|
|
|
+ <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
|
|
|
+ };
|
|
|
+
|
|
|
+ mem {
|
|
|
+ polling-delay-passive = <1000>;
|
|
|
+ polling-delay = <1000>;
|
|
|
+
|
|
|
+ thermal-sensors =
|
|
|
+ <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
|
|
|
+ };
|
|
|
+
|
|
|
+ gpu {
|
|
|
+ polling-delay-passive = <1000>;
|
|
|
+ polling-delay = <1000>;
|
|
|
+
|
|
|
+ thermal-sensors =
|
|
|
+ <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
|
|
|
+ };
|
|
|
+
|
|
|
+ pllx {
|
|
|
+ polling-delay-passive = <1000>;
|
|
|
+ polling-delay = <1000>;
|
|
|
+
|
|
|
+ thermal-sensors =
|
|
|
+ <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ timer {
|
|
|
+ compatible = "arm,armv7-timer";
|
|
|
+ interrupts = <GIC_PPI 13
|
|
|
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
|
+ <GIC_PPI 14
|
|
|
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
|
+ <GIC_PPI 11
|
|
|
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
|
+ <GIC_PPI 10
|
|
|
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
|
+ interrupt-parent = <&gic>;
|
|
|
+ };
|
|
|
};
|