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@@ -76,9 +76,7 @@
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SPICR_SPE)
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#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
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-#ifndef CONFIG_XILINX_SPI_IDLE_VAL
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-#define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0)
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-#endif
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+#define XILINX_SPI_IDLE_VAL GENMASK(7, 0)
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#define XILINX_SPISR_TIMEOUT 10000 /* in milliseconds */
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@@ -176,7 +174,7 @@ static u32 xilinx_spi_fill_txfifo(struct udevice *bus, const u8 *txp,
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while (txbytes && !(readl(®s->spisr) & SPISR_TX_FULL) &&
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i < priv->fifo_depth) {
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- d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
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+ d = txp ? *txp++ : XILINX_SPI_IDLE_VAL;
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debug("spi_xfer: tx:%x ", d);
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/* write out and wait for processing (receive data) */
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writel(d & SPIDTR_8BIT_MASK, ®s->spidtr);
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