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@@ -0,0 +1,131 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Watchdog driver for SBSA
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+ *
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+ * Copyright 2020 NXP
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+ */
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+
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+#include <asm/io.h>
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+#include <common.h>
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+#include <dm/device.h>
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+#include <dm/fdtaddr.h>
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+#include <dm/read.h>
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+#include <linux/bitops.h>
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+#include <linux/err.h>
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+#include <watchdog.h>
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+#include <wdt.h>
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+/* SBSA Generic Watchdog register definitions */
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+/* refresh frame */
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+#define SBSA_GWDT_WRR 0x000
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+
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+/* control frame */
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+#define SBSA_GWDT_WCS 0x000
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+#define SBSA_GWDT_WOR 0x008
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+#define SBSA_GWDT_WCV 0x010
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+
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+/* refresh/control frame */
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+#define SBSA_GWDT_W_IIDR 0xfcc
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+#define SBSA_GWDT_IDR 0xfd0
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+
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+/* Watchdog Control and Status Register */
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+#define SBSA_GWDT_WCS_EN BIT(0)
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+#define SBSA_GWDT_WCS_WS0 BIT(1)
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+#define SBSA_GWDT_WCS_WS1 BIT(2)
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+
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+struct sbsa_gwdt_priv {
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+ void __iomem *reg_refresh;
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+ void __iomem *reg_control;
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+};
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+
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+static int sbsa_gwdt_reset(struct udevice *dev)
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+{
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+ struct sbsa_gwdt_priv *priv = dev_get_priv(dev);
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+
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+ writel(0, priv->reg_refresh + SBSA_GWDT_WRR);
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+
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+ return 0;
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+}
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+
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+static int sbsa_gwdt_start(struct udevice *dev, u64 timeout, ulong flags)
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+{
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+ struct sbsa_gwdt_priv *priv = dev_get_priv(dev);
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+ u32 clk;
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+
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+ /*
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+ * it work in the single stage mode in u-boot,
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+ * The first signal (WS0) is ignored,
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+ * the timeout is (WOR * 2), so the WOR should be configured
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+ * to half value of timeout.
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+ */
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+ clk = get_tbclk();
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+ writel(clk / 2 * timeout,
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+ priv->reg_control + SBSA_GWDT_WOR);
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+
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+ /* writing WCS will cause an explicit watchdog refresh */
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+ writel(SBSA_GWDT_WCS_EN, priv->reg_control + SBSA_GWDT_WCS);
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+
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+ return 0;
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+}
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+
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+static int sbsa_gwdt_stop(struct udevice *dev)
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+{
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+ struct sbsa_gwdt_priv *priv = dev_get_priv(dev);
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+
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+ writel(0, priv->reg_control + SBSA_GWDT_WCS);
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+
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+ return 0;
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+}
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+
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+static int sbsa_gwdt_expire_now(struct udevice *dev, ulong flags)
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+{
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+ sbsa_gwdt_start(dev, 0, flags);
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+
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+ return 0;
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+}
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+
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+static int sbsa_gwdt_probe(struct udevice *dev)
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+{
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+ debug("%s: Probing wdt%u (sbsa-gwdt)\n", __func__, dev->seq);
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+
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+ return 0;
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+}
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+
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+static int sbsa_gwdt_ofdata_to_platdata(struct udevice *dev)
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+{
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+ struct sbsa_gwdt_priv *priv = dev_get_priv(dev);
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+
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+ priv->reg_control = (void __iomem *)dev_read_addr_index(dev, 0);
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+ if (IS_ERR(priv->reg_control))
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+ return PTR_ERR(priv->reg_control);
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+
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+ priv->reg_refresh = (void __iomem *)dev_read_addr_index(dev, 1);
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+ if (IS_ERR(priv->reg_refresh))
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+ return PTR_ERR(priv->reg_refresh);
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+
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+ return 0;
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+}
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+
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+static const struct wdt_ops sbsa_gwdt_ops = {
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+ .start = sbsa_gwdt_start,
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+ .reset = sbsa_gwdt_reset,
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+ .stop = sbsa_gwdt_stop,
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+ .expire_now = sbsa_gwdt_expire_now,
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+};
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+
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+static const struct udevice_id sbsa_gwdt_ids[] = {
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+ { .compatible = "arm,sbsa-gwdt" },
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+ {}
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+};
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+
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+U_BOOT_DRIVER(sbsa_gwdt) = {
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+ .name = "sbsa_gwdt",
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+ .id = UCLASS_WDT,
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+ .of_match = sbsa_gwdt_ids,
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+ .probe = sbsa_gwdt_probe,
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+ .priv_auto_alloc_size = sizeof(struct sbsa_gwdt_priv),
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+ .ofdata_to_platdata = sbsa_gwdt_ofdata_to_platdata,
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+ .ops = &sbsa_gwdt_ops,
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+};
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