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@@ -502,15 +502,22 @@ static void set_sysctl(struct mmc *mmc, uint clock)
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clk = (pre_div << 8) | (div << 4);
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+#ifdef CONFIG_FSL_USDHC
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+ esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
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+#else
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esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
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+#endif
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esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
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udelay(10000);
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- clk = SYSCTL_PEREN | SYSCTL_CKEN;
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+#ifdef CONFIG_FSL_USDHC
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+ esdhc_clrbits32(®s->sysctl, SYSCTL_RSTA);
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+#else
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+ esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
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+#endif
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- esdhc_setbits32(®s->sysctl, clk);
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}
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#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
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@@ -585,7 +592,9 @@ static int esdhc_init(struct mmc *mmc)
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esdhc_write32(®s->scr, 0x00000040);
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#endif
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+#ifndef CONFIG_FSL_USDHC
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esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
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+#endif
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/* Set the initial clock speed */
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mmc_set_clock(mmc, 400000);
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@@ -657,8 +666,10 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
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/* First reset the eSDHC controller */
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esdhc_reset(regs);
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+#ifndef CONFIG_FSL_USDHC
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esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
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| SYSCTL_IPGEN | SYSCTL_CKEN);
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+#endif
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writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
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memset(&cfg->cfg, 0, sizeof(cfg->cfg));
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