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@@ -8,23 +8,80 @@
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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+#include <syscon.h>
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#include <linux/io.h>
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#include <mach/at91_pmc.h>
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+#include <mach/sama5_sfr.h>
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#include "pmc.h"
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DECLARE_GLOBAL_DATA_PTR;
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-#define UTMI_FIXED_MUL 40
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+/*
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+ * The purpose of this clock is to generate a 480 MHz signal. A different
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+ * rate can't be configured.
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+ */
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+#define UTMI_RATE 480000000
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static int utmi_clk_enable(struct clk *clk)
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{
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struct pmc_platdata *plat = dev_get_platdata(clk->dev);
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struct at91_pmc *pmc = plat->reg_base;
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+ struct clk clk_dev;
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+ ulong clk_rate;
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+ u32 utmi_ref_clk_freq;
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u32 tmp;
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+ int err;
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if (readl(&pmc->sr) & AT91_PMC_LOCKU)
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return 0;
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+ /*
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+ * If mainck rate is different from 12 MHz, we have to configure the
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+ * FREQ field of the SFR_UTMICKTRIM register to generate properly
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+ * the utmi clock.
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+ */
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+ err = clk_get_by_index(clk->dev, 0, &clk_dev);
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+ if (err)
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+ return -EINVAL;
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+
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+ clk_rate = clk_get_rate(&clk_dev);
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+ switch (clk_rate) {
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+ case 12000000:
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+ utmi_ref_clk_freq = 0;
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+ break;
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+ case 16000000:
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+ utmi_ref_clk_freq = 1;
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+ break;
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+ case 24000000:
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+ utmi_ref_clk_freq = 2;
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+ break;
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+ /*
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+ * Not supported on SAMA5D2 but it's not an issue since MAINCK
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+ * maximum value is 24 MHz.
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+ */
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+ case 48000000:
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+ utmi_ref_clk_freq = 3;
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+ break;
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+ default:
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+ printf("UTMICK: unsupported mainck rate\n");
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+ return -EINVAL;
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+ }
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+
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+ if (plat->regmap_sfr) {
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+ err = regmap_read(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, &tmp);
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+ if (err)
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+ return -EINVAL;
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+
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+ tmp &= ~AT91_UTMICKTRIM_FREQ;
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+ tmp |= utmi_ref_clk_freq;
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+ err = regmap_write(plat->regmap_sfr, AT91_SFR_UTMICKTRIM, tmp);
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+ if (err)
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+ return -EINVAL;
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+ } else if (utmi_ref_clk_freq) {
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+ printf("UTMICK: sfr node required\n");
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+ return -EINVAL;
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+ }
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+
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tmp = readl(&pmc->uckr);
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tmp |= AT91_PMC_UPLLEN |
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AT91_PMC_UPLLCOUNT |
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@@ -39,7 +96,8 @@ static int utmi_clk_enable(struct clk *clk)
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static ulong utmi_clk_get_rate(struct clk *clk)
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{
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- return gd->arch.main_clk_rate_hz * UTMI_FIXED_MUL;
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+ /* UTMI clk rate is fixed. */
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+ return UTMI_RATE;
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}
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static struct clk_ops utmi_clk_ops = {
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@@ -47,6 +105,20 @@ static struct clk_ops utmi_clk_ops = {
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.get_rate = utmi_clk_get_rate,
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};
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+static int utmi_clk_ofdata_to_platdata(struct udevice *dev)
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+{
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+ struct pmc_platdata *plat = dev_get_platdata(dev);
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+ struct udevice *syscon;
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+
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+ uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
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+ "regmap-sfr", &syscon);
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+
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+ if (syscon)
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+ plat->regmap_sfr = syscon_get_regmap(syscon);
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+
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+ return 0;
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+}
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+
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static int utmi_clk_probe(struct udevice *dev)
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{
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return at91_pmc_core_probe(dev);
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@@ -62,6 +134,7 @@ U_BOOT_DRIVER(at91sam9x5_utmi_clk) = {
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.id = UCLASS_CLK,
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.of_match = utmi_clk_match,
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.probe = utmi_clk_probe,
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+ .ofdata_to_platdata = utmi_clk_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct pmc_platdata),
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.ops = &utmi_clk_ops,
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};
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