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@@ -0,0 +1,26 @@
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+Xilinx Zynq QSPI controller Device Tree Bindings
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+-------------------------------------------------
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+
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+Required properties:
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+- compatible : Should be "xlnx,zynq-qspi-1.0".
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+- reg : Physical base address and size of QSPI registers map.
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+- interrupts : Property with a value describing the interrupt
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+ number.
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+- interrupt-parent : Must be core interrupt controller
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+- clock-names : List of input clock names - "ref_clk", "pclk"
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+ (See clock bindings for details).
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+- clocks : Clock phandles (see clock bindings for details).
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+
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+Optional properties:
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+- num-cs : Number of chip selects used.
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+
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+Example:
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+ qspi@e000d000 {
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+ compatible = "xlnx,zynq-qspi-1.0";
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+ clock-names = "ref_clk", "pclk";
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+ clocks = <&clkc 10>, <&clkc 43>;
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+ interrupt-parent = <&intc>;
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+ interrupts = <0 19 4>;
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+ num-cs = <1>;
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+ reg = <0xe000d000 0x1000>;
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+ } ;
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