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xilinx: r5: Fix MPU setting for R5

Map all resource for R5 to operate properly.
The patch is done based on the commit 23f7b1a77602 ("armv7R: K3: am654:
Enable MPU regions") which also map the whole 4GB at first and then change
mapping for DDR.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek 3 years ago
parent
commit
e3259a700a
1 changed files with 4 additions and 7 deletions
  1. 4 7
      arch/arm/mach-zynqmp-r5/cpu.c

+ 4 - 7
arch/arm/mach-zynqmp-r5/cpu.c

@@ -11,11 +11,9 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 struct mpu_region_config region_config[] = {
-	{ 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
-	  O_I_WB_RD_WR_ALLOC, REGION_1GB },
-	{ 0x20000000, REGION_1, XN_EN, PRIV_RO_USR_RO,
-	  O_I_WB_RD_WR_ALLOC, REGION_512MB },
-	{ 0x40000000, REGION_2, XN_EN, PRIV_RO_USR_RO,
+	{ 0x00000000, REGION_0, XN_EN, PRIV_RW_USR_RW,
+	  SHARED_WRITE_BUFFERED, REGION_4GB },
+	{ 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
 	  O_I_WB_RD_WR_ALLOC, REGION_1GB },
 };
 
@@ -23,8 +21,7 @@ int arch_cpu_init(void)
 {
 	gd->cpu_clk = CONFIG_CPU_FREQ_HZ;
 
-	setup_mpu_regions(region_config, sizeof(region_config) /
-			  sizeof(struct mpu_region_config));
+	setup_mpu_regions(region_config, ARRAY_SIZE(region_config));
 
 	return 0;
 }