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@@ -0,0 +1,74 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * (C)Copyright 2016 Rockchip Electronics Co., Ltd
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+ * Authors: Andy Yan <andy.yan@rock-chips.com>
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+ */
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+
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+#include <common.h>
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+#include <asm/io.h>
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+#include <fdtdec.h>
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+#include <asm/arch/grf_rv1108.h>
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+#include <asm/arch/hardware.h>
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+#include <asm/gpio.h>
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+int mach_cpu_init(void)
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+{
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+ int node;
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+ struct rv1108_grf *grf;
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+ enum {
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+ GPIO3C3_SHIFT = 6,
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+ GPIO3C3_MASK = 3 << GPIO3C3_SHIFT,
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+
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+ GPIO3C2_SHIFT = 4,
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+ GPIO3C2_MASK = 3 << GPIO3C2_SHIFT,
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+
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+ GPIO2D2_SHIFT = 4,
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+ GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
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+ GPIO2D2_GPIO = 0,
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+ GPIO2D2_UART2_SOUT_M0,
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+
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+ GPIO2D1_SHIFT = 2,
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+ GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
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+ GPIO2D1_GPIO = 0,
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+ GPIO2D1_UART2_SIN_M0,
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+ };
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+
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+ node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "rockchip,rv1108-grf");
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+ grf = (struct rv1108_grf *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
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+
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+ /* Elgin board use UART2 m0 for debug*/
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+ rk_clrsetreg(&grf->gpio2d_iomux,
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+ GPIO2D2_MASK | GPIO2D1_MASK,
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+ GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
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+ GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
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+ rk_clrreg(&grf->gpio3c_iomux, GPIO3C3_MASK | GPIO3C2_MASK);
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+
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+ return 0;
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+}
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+
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+#define MODEM_ENABLE_GPIO 111
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+
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+int board_init(void)
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+{
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+ gpio_request(MODEM_ENABLE_GPIO, "modem_enable");
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+ gpio_direction_output(MODEM_ENABLE_GPIO, 0);
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+
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+ return 0;
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+}
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+
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+int dram_init(void)
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+{
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+ gd->ram_size = 0x8000000;
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+
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+ return 0;
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+}
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+
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+int dram_init_banksize(void)
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+{
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+ gd->bd->bi_dram[0].start = 0x60000000;
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+ gd->bd->bi_dram[0].size = 0x8000000;
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+
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+ return 0;
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+}
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