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@@ -73,6 +73,7 @@
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#define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000))
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#define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000))
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#define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000))
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+#define MVEBU_DFX_BASE (MVEBU_REGISTER(0xe4000))
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#define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200))
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#define MBUS_ERR_PROP_EN (1 << 8)
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@@ -92,6 +93,7 @@
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#define SPI_PUP_EN BIT(5)
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#define MVEBU_CORE_DIV_CLK_CTRL(i) (MVEBU_CLOCK_BASE + ((i) * 0x8))
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+#define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0x250 + ((i) * 0x4))
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#define NAND_ECC_DIVCKL_RATIO_OFFS 8
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#define NAND_ECC_DIVCKL_RATIO_MASK (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
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