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@@ -170,6 +170,17 @@ static int phy_unprepare(struct tegra_xusb_phy *phy)
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return tegra_xusb_padctl_disable(phy->padctl);
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}
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+#define XUSB_PADCTL_USB3_PAD_MUX 0x28
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+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE (1 << 0)
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+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0 (1 << 1)
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+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1 (1 << 2)
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+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2 (1 << 3)
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+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3 (1 << 4)
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+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4 (1 << 5)
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+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5 (1 << 6)
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+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6 (1 << 7)
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+#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0 (1 << 8)
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+
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20)
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#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20)
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@@ -366,31 +377,6 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
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value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
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padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
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- value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
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- value &= ~CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;
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- value &= ~CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;
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- value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;
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- value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
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- writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
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-
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- value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
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- value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
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- padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
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-
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- value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
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- value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
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- padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
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-
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- value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
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- value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
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- padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
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-
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- udelay(1);
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-
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- value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
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- value |= CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE;
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- writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
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-
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debug("< %s()\n", __func__);
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return 0;
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}
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@@ -454,3 +440,35 @@ void tegra_xusb_padctl_init(void)
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ret = tegra_xusb_process_nodes(nodes, count, &tegra210_socdata);
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debug("%s: done, ret=%d\n", __func__, ret);
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}
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+
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+void tegra_xusb_padctl_exit(void)
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+{
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+ u32 value;
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+
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+ debug("> %s\n", __func__);
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+
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+ value = padctl_readl(&padctl, XUSB_PADCTL_USB3_PAD_MUX);
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+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE;
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+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0;
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+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1;
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+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2;
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+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3;
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+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4;
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+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5;
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+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6;
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+ value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0;
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+ padctl_writel(&padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
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+
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+ value = padctl_readl(&padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
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+ value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ;
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+ value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK;
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+ value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(3);
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+ value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE;
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+ padctl_writel(&padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
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+
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+ reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1);
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+ while (padctl.enable)
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+ tegra_xusb_padctl_disable(&padctl);
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+
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+ debug("< %s()\n", __func__);
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+}
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