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@@ -0,0 +1,501 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Copyright (C) 2018 Exceet Electronics GmbH
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+ * Copyright (C) 2018 Bootlin
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+ *
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+ * Author: Boris Brezillon <boris.brezillon@bootlin.com>
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+ */
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+
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+#ifndef __UBOOT__
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+#include <linux/dmaengine.h>
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+#include <linux/pm_runtime.h>
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+#include "internals.h"
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+#else
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+#include <spi.h>
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+#include <spi-mem.h>
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+#endif
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+
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+#ifndef __UBOOT__
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+/**
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+ * spi_controller_dma_map_mem_op_data() - DMA-map the buffer attached to a
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+ * memory operation
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+ * @ctlr: the SPI controller requesting this dma_map()
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+ * @op: the memory operation containing the buffer to map
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+ * @sgt: a pointer to a non-initialized sg_table that will be filled by this
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+ * function
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+ *
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+ * Some controllers might want to do DMA on the data buffer embedded in @op.
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+ * This helper prepares everything for you and provides a ready-to-use
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+ * sg_table. This function is not intended to be called from spi drivers.
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+ * Only SPI controller drivers should use it.
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+ * Note that the caller must ensure the memory region pointed by
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+ * op->data.buf.{in,out} is DMA-able before calling this function.
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+ *
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+ * Return: 0 in case of success, a negative error code otherwise.
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+ */
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+int spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,
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+ const struct spi_mem_op *op,
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+ struct sg_table *sgt)
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+{
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+ struct device *dmadev;
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+
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+ if (!op->data.nbytes)
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+ return -EINVAL;
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+
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+ if (op->data.dir == SPI_MEM_DATA_OUT && ctlr->dma_tx)
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+ dmadev = ctlr->dma_tx->device->dev;
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+ else if (op->data.dir == SPI_MEM_DATA_IN && ctlr->dma_rx)
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+ dmadev = ctlr->dma_rx->device->dev;
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+ else
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+ dmadev = ctlr->dev.parent;
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+
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+ if (!dmadev)
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+ return -EINVAL;
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+
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+ return spi_map_buf(ctlr, dmadev, sgt, op->data.buf.in, op->data.nbytes,
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+ op->data.dir == SPI_MEM_DATA_IN ?
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+ DMA_FROM_DEVICE : DMA_TO_DEVICE);
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+}
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+EXPORT_SYMBOL_GPL(spi_controller_dma_map_mem_op_data);
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+
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+/**
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+ * spi_controller_dma_unmap_mem_op_data() - DMA-unmap the buffer attached to a
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+ * memory operation
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+ * @ctlr: the SPI controller requesting this dma_unmap()
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+ * @op: the memory operation containing the buffer to unmap
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+ * @sgt: a pointer to an sg_table previously initialized by
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+ * spi_controller_dma_map_mem_op_data()
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+ *
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+ * Some controllers might want to do DMA on the data buffer embedded in @op.
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+ * This helper prepares things so that the CPU can access the
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+ * op->data.buf.{in,out} buffer again.
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+ *
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+ * This function is not intended to be called from SPI drivers. Only SPI
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+ * controller drivers should use it.
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+ *
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+ * This function should be called after the DMA operation has finished and is
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+ * only valid if the previous spi_controller_dma_map_mem_op_data() call
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+ * returned 0.
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+ *
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+ * Return: 0 in case of success, a negative error code otherwise.
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+ */
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+void spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr,
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+ const struct spi_mem_op *op,
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+ struct sg_table *sgt)
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+{
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+ struct device *dmadev;
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+
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+ if (!op->data.nbytes)
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+ return;
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+
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+ if (op->data.dir == SPI_MEM_DATA_OUT && ctlr->dma_tx)
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+ dmadev = ctlr->dma_tx->device->dev;
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+ else if (op->data.dir == SPI_MEM_DATA_IN && ctlr->dma_rx)
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+ dmadev = ctlr->dma_rx->device->dev;
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+ else
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+ dmadev = ctlr->dev.parent;
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+
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+ spi_unmap_buf(ctlr, dmadev, sgt,
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+ op->data.dir == SPI_MEM_DATA_IN ?
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+ DMA_FROM_DEVICE : DMA_TO_DEVICE);
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+}
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+EXPORT_SYMBOL_GPL(spi_controller_dma_unmap_mem_op_data);
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+#endif /* __UBOOT__ */
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+
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+static int spi_check_buswidth_req(struct spi_slave *slave, u8 buswidth, bool tx)
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+{
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+ u32 mode = slave->mode;
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+
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+ switch (buswidth) {
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+ case 1:
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+ return 0;
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+
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+ case 2:
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+ if ((tx && (mode & (SPI_TX_DUAL | SPI_TX_QUAD))) ||
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+ (!tx && (mode & (SPI_RX_DUAL | SPI_RX_QUAD))))
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+ return 0;
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+
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+ break;
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+
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+ case 4:
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+ if ((tx && (mode & SPI_TX_QUAD)) ||
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+ (!tx && (mode & SPI_RX_QUAD)))
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+ return 0;
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+
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+ break;
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+
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+ default:
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+ break;
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+ }
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+
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+ return -ENOTSUPP;
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+}
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+
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+bool spi_mem_default_supports_op(struct spi_slave *slave,
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+ const struct spi_mem_op *op)
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+{
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+ if (spi_check_buswidth_req(slave, op->cmd.buswidth, true))
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+ return false;
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+
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+ if (op->addr.nbytes &&
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+ spi_check_buswidth_req(slave, op->addr.buswidth, true))
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+ return false;
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+
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+ if (op->dummy.nbytes &&
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+ spi_check_buswidth_req(slave, op->dummy.buswidth, true))
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+ return false;
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+
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+ if (op->data.nbytes &&
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+ spi_check_buswidth_req(slave, op->data.buswidth,
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+ op->data.dir == SPI_MEM_DATA_OUT))
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+ return false;
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+
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+ return true;
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+}
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+EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
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+
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+/**
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+ * spi_mem_supports_op() - Check if a memory device and the controller it is
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+ * connected to support a specific memory operation
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+ * @slave: the SPI device
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+ * @op: the memory operation to check
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+ *
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+ * Some controllers are only supporting Single or Dual IOs, others might only
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+ * support specific opcodes, or it can even be that the controller and device
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+ * both support Quad IOs but the hardware prevents you from using it because
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+ * only 2 IO lines are connected.
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+ *
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+ * This function checks whether a specific operation is supported.
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+ *
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+ * Return: true if @op is supported, false otherwise.
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+ */
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+bool spi_mem_supports_op(struct spi_slave *slave,
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+ const struct spi_mem_op *op)
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+{
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+ struct udevice *bus = slave->dev->parent;
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+ struct dm_spi_ops *ops = spi_get_ops(bus);
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+
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+ if (ops->mem_ops && ops->mem_ops->supports_op)
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+ return ops->mem_ops->supports_op(slave, op);
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+
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+ return spi_mem_default_supports_op(slave, op);
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+}
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+EXPORT_SYMBOL_GPL(spi_mem_supports_op);
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+
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+/**
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+ * spi_mem_exec_op() - Execute a memory operation
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+ * @slave: the SPI device
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+ * @op: the memory operation to execute
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+ *
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+ * Executes a memory operation.
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+ *
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+ * This function first checks that @op is supported and then tries to execute
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+ * it.
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+ *
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+ * Return: 0 in case of success, a negative error code otherwise.
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+ */
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+int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
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+{
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+ struct udevice *bus = slave->dev->parent;
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+ struct dm_spi_ops *ops = spi_get_ops(bus);
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+ unsigned int pos = 0;
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+ const u8 *tx_buf = NULL;
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+ u8 *rx_buf = NULL;
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+ u8 *op_buf;
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+ int op_len;
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+ u32 flag;
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+ int ret;
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+ int i;
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+
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+ if (!spi_mem_supports_op(slave, op))
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+ return -ENOTSUPP;
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+
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+ if (ops->mem_ops) {
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+#ifndef __UBOOT__
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+ /*
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+ * Flush the message queue before executing our SPI memory
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+ * operation to prevent preemption of regular SPI transfers.
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+ */
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+ spi_flush_queue(ctlr);
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+
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+ if (ctlr->auto_runtime_pm) {
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+ ret = pm_runtime_get_sync(ctlr->dev.parent);
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+ if (ret < 0) {
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+ dev_err(&ctlr->dev,
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+ "Failed to power device: %d\n",
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+ ret);
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+ return ret;
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+ }
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+ }
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+
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+ mutex_lock(&ctlr->bus_lock_mutex);
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+ mutex_lock(&ctlr->io_mutex);
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+#endif
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+ ret = ops->mem_ops->exec_op(slave, op);
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+#ifndef __UBOOT__
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+ mutex_unlock(&ctlr->io_mutex);
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+ mutex_unlock(&ctlr->bus_lock_mutex);
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+
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+ if (ctlr->auto_runtime_pm)
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+ pm_runtime_put(ctlr->dev.parent);
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+#endif
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+
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+ /*
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+ * Some controllers only optimize specific paths (typically the
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+ * read path) and expect the core to use the regular SPI
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+ * interface in other cases.
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+ */
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+ if (!ret || ret != -ENOTSUPP)
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+ return ret;
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+ }
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+
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+#ifndef __UBOOT__
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+ tmpbufsize = sizeof(op->cmd.opcode) + op->addr.nbytes +
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+ op->dummy.nbytes;
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+
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+ /*
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+ * Allocate a buffer to transmit the CMD, ADDR cycles with kmalloc() so
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+ * we're guaranteed that this buffer is DMA-able, as required by the
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+ * SPI layer.
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+ */
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+ tmpbuf = kzalloc(tmpbufsize, GFP_KERNEL | GFP_DMA);
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+ if (!tmpbuf)
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+ return -ENOMEM;
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+
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+ spi_message_init(&msg);
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+
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+ tmpbuf[0] = op->cmd.opcode;
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+ xfers[xferpos].tx_buf = tmpbuf;
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+ xfers[xferpos].len = sizeof(op->cmd.opcode);
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+ xfers[xferpos].tx_nbits = op->cmd.buswidth;
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+ spi_message_add_tail(&xfers[xferpos], &msg);
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+ xferpos++;
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+ totalxferlen++;
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+
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+ if (op->addr.nbytes) {
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+ int i;
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+
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+ for (i = 0; i < op->addr.nbytes; i++)
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+ tmpbuf[i + 1] = op->addr.val >>
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+ (8 * (op->addr.nbytes - i - 1));
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+
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+ xfers[xferpos].tx_buf = tmpbuf + 1;
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+ xfers[xferpos].len = op->addr.nbytes;
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+ xfers[xferpos].tx_nbits = op->addr.buswidth;
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+ spi_message_add_tail(&xfers[xferpos], &msg);
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+ xferpos++;
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+ totalxferlen += op->addr.nbytes;
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+ }
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+
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+ if (op->dummy.nbytes) {
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+ memset(tmpbuf + op->addr.nbytes + 1, 0xff, op->dummy.nbytes);
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+ xfers[xferpos].tx_buf = tmpbuf + op->addr.nbytes + 1;
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+ xfers[xferpos].len = op->dummy.nbytes;
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+ xfers[xferpos].tx_nbits = op->dummy.buswidth;
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+ spi_message_add_tail(&xfers[xferpos], &msg);
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+ xferpos++;
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+ totalxferlen += op->dummy.nbytes;
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+ }
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+
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+ if (op->data.nbytes) {
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+ if (op->data.dir == SPI_MEM_DATA_IN) {
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+ xfers[xferpos].rx_buf = op->data.buf.in;
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+ xfers[xferpos].rx_nbits = op->data.buswidth;
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+ } else {
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+ xfers[xferpos].tx_buf = op->data.buf.out;
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+ xfers[xferpos].tx_nbits = op->data.buswidth;
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+ }
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+
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+ xfers[xferpos].len = op->data.nbytes;
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+ spi_message_add_tail(&xfers[xferpos], &msg);
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+ xferpos++;
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+ totalxferlen += op->data.nbytes;
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+ }
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+
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+ ret = spi_sync(slave, &msg);
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+
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+ kfree(tmpbuf);
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+
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+ if (ret)
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+ return ret;
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+
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+ if (msg.actual_length != totalxferlen)
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+ return -EIO;
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+#else
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+
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+ /* U-Boot does not support parallel SPI data lanes */
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+ if ((op->cmd.buswidth != 1) ||
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+ (op->addr.nbytes && op->addr.buswidth != 1) ||
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+ (op->dummy.nbytes && op->dummy.buswidth != 1) ||
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+ (op->data.nbytes && op->data.buswidth != 1)) {
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+ printf("Dual/Quad raw SPI transfers not supported\n");
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+ return -ENOTSUPP;
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+ }
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+
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+ if (op->data.nbytes) {
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+ if (op->data.dir == SPI_MEM_DATA_IN)
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+ rx_buf = op->data.buf.in;
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+ else
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+ tx_buf = op->data.buf.out;
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+ }
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+
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+ op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
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+ op_buf = calloc(1, op_len);
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+
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+ ret = spi_claim_bus(slave);
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+ if (ret < 0)
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+ return ret;
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+
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+ op_buf[pos++] = op->cmd.opcode;
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+
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+ if (op->addr.nbytes) {
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+ for (i = 0; i < op->addr.nbytes; i++)
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+ op_buf[pos + i] = op->addr.val >>
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+ (8 * (op->addr.nbytes - i - 1));
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+
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+ pos += op->addr.nbytes;
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+ }
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+
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+ if (op->dummy.nbytes)
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+ memset(op_buf + pos, 0xff, op->dummy.nbytes);
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+
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+ /* 1st transfer: opcode + address + dummy cycles */
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+ flag = SPI_XFER_BEGIN;
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+ /* Make sure to set END bit if no tx or rx data messages follow */
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+ if (!tx_buf && !rx_buf)
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+ flag |= SPI_XFER_END;
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+
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+ ret = spi_xfer(slave, op_len * 8, op_buf, NULL, flag);
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+ if (ret)
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+ return ret;
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+
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+ /* 2nd transfer: rx or tx data path */
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+ if (tx_buf || rx_buf) {
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+ ret = spi_xfer(slave, op->data.nbytes * 8, tx_buf,
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+ rx_buf, SPI_XFER_END);
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+ if (ret)
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+ return ret;
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+ }
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+
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+ spi_release_bus(slave);
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+
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+ for (i = 0; i < pos; i++)
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+ debug("%02x ", op_buf[i]);
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+ debug("| [%dB %s] ",
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+ tx_buf || rx_buf ? op->data.nbytes : 0,
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+ tx_buf || rx_buf ? (tx_buf ? "out" : "in") : "-");
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+ for (i = 0; i < op->data.nbytes; i++)
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+ debug("%02x ", tx_buf ? tx_buf[i] : rx_buf[i]);
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+ debug("[ret %d]\n", ret);
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+
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+ free(op_buf);
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+
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+ if (ret < 0)
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+ return ret;
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+#endif /* __UBOOT__ */
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+
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+ return 0;
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+}
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|
+EXPORT_SYMBOL_GPL(spi_mem_exec_op);
|
|
|
+
|
|
|
+/**
|
|
|
+ * spi_mem_adjust_op_size() - Adjust the data size of a SPI mem operation to
|
|
|
+ * match controller limitations
|
|
|
+ * @slave: the SPI device
|
|
|
+ * @op: the operation to adjust
|
|
|
+ *
|
|
|
+ * Some controllers have FIFO limitations and must split a data transfer
|
|
|
+ * operation into multiple ones, others require a specific alignment for
|
|
|
+ * optimized accesses. This function allows SPI mem drivers to split a single
|
|
|
+ * operation into multiple sub-operations when required.
|
|
|
+ *
|
|
|
+ * Return: a negative error code if the controller can't properly adjust @op,
|
|
|
+ * 0 otherwise. Note that @op->data.nbytes will be updated if @op
|
|
|
+ * can't be handled in a single step.
|
|
|
+ */
|
|
|
+int spi_mem_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op)
|
|
|
+{
|
|
|
+ struct udevice *bus = slave->dev->parent;
|
|
|
+ struct dm_spi_ops *ops = spi_get_ops(bus);
|
|
|
+
|
|
|
+ if (ops->mem_ops && ops->mem_ops->adjust_op_size)
|
|
|
+ return ops->mem_ops->adjust_op_size(slave, op);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+EXPORT_SYMBOL_GPL(spi_mem_adjust_op_size);
|
|
|
+
|
|
|
+#ifndef __UBOOT__
|
|
|
+static inline struct spi_mem_driver *to_spi_mem_drv(struct device_driver *drv)
|
|
|
+{
|
|
|
+ return container_of(drv, struct spi_mem_driver, spidrv.driver);
|
|
|
+}
|
|
|
+
|
|
|
+static int spi_mem_probe(struct spi_device *spi)
|
|
|
+{
|
|
|
+ struct spi_mem_driver *memdrv = to_spi_mem_drv(spi->dev.driver);
|
|
|
+ struct spi_mem *mem;
|
|
|
+
|
|
|
+ mem = devm_kzalloc(&spi->dev, sizeof(*mem), GFP_KERNEL);
|
|
|
+ if (!mem)
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ mem->spi = spi;
|
|
|
+ spi_set_drvdata(spi, mem);
|
|
|
+
|
|
|
+ return memdrv->probe(mem);
|
|
|
+}
|
|
|
+
|
|
|
+static int spi_mem_remove(struct spi_device *spi)
|
|
|
+{
|
|
|
+ struct spi_mem_driver *memdrv = to_spi_mem_drv(spi->dev.driver);
|
|
|
+ struct spi_mem *mem = spi_get_drvdata(spi);
|
|
|
+
|
|
|
+ if (memdrv->remove)
|
|
|
+ return memdrv->remove(mem);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void spi_mem_shutdown(struct spi_device *spi)
|
|
|
+{
|
|
|
+ struct spi_mem_driver *memdrv = to_spi_mem_drv(spi->dev.driver);
|
|
|
+ struct spi_mem *mem = spi_get_drvdata(spi);
|
|
|
+
|
|
|
+ if (memdrv->shutdown)
|
|
|
+ memdrv->shutdown(mem);
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * spi_mem_driver_register_with_owner() - Register a SPI memory driver
|
|
|
+ * @memdrv: the SPI memory driver to register
|
|
|
+ * @owner: the owner of this driver
|
|
|
+ *
|
|
|
+ * Registers a SPI memory driver.
|
|
|
+ *
|
|
|
+ * Return: 0 in case of success, a negative error core otherwise.
|
|
|
+ */
|
|
|
+
|
|
|
+int spi_mem_driver_register_with_owner(struct spi_mem_driver *memdrv,
|
|
|
+ struct module *owner)
|
|
|
+{
|
|
|
+ memdrv->spidrv.probe = spi_mem_probe;
|
|
|
+ memdrv->spidrv.remove = spi_mem_remove;
|
|
|
+ memdrv->spidrv.shutdown = spi_mem_shutdown;
|
|
|
+
|
|
|
+ return __spi_register_driver(owner, &memdrv->spidrv);
|
|
|
+}
|
|
|
+EXPORT_SYMBOL_GPL(spi_mem_driver_register_with_owner);
|
|
|
+
|
|
|
+/**
|
|
|
+ * spi_mem_driver_unregister_with_owner() - Unregister a SPI memory driver
|
|
|
+ * @memdrv: the SPI memory driver to unregister
|
|
|
+ *
|
|
|
+ * Unregisters a SPI memory driver.
|
|
|
+ */
|
|
|
+void spi_mem_driver_unregister(struct spi_mem_driver *memdrv)
|
|
|
+{
|
|
|
+ spi_unregister_driver(&memdrv->spidrv);
|
|
|
+}
|
|
|
+EXPORT_SYMBOL_GPL(spi_mem_driver_unregister);
|
|
|
+#endif /* __UBOOT__ */
|