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clk: sifive: Factor-out PLL library as separate module

To match SiFive clock driver with latest Linux, we factor-out PLL
library as separate module under drivers/clk/analogbits.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Anup Patel 5 years ago
parent
commit
d04c79d2b2

+ 1 - 0
drivers/clk/Kconfig

@@ -98,6 +98,7 @@ config CLK_STM32MP1
 	  Enable the STM32 clock (RCC) driver. Enable support for
 	  manipulating STM32MP1's on-SoC clocks.
 
+source "drivers/clk/analogbits/Kconfig"
 source "drivers/clk/at91/Kconfig"
 source "drivers/clk/exynos/Kconfig"
 source "drivers/clk/imx/Kconfig"

+ 1 - 0
drivers/clk/Makefile

@@ -8,6 +8,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o
 obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o
 obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o
 
+obj-y += analogbits/
 obj-y += imx/
 obj-y += tegra/
 obj-$(CONFIG_ARCH_ASPEED) += aspeed/

+ 4 - 0
drivers/clk/analogbits/Kconfig

@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config CLK_ANALOGBITS_WRPLL_CLN28HPC
+	bool

+ 3 - 0
drivers/clk/analogbits/Makefile

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC)	+= wrpll-cln28hpc.o

+ 1 - 2
drivers/clk/sifive/wrpll-cln28hpc.c → drivers/clk/analogbits/wrpll-cln28hpc.c

@@ -35,8 +35,7 @@
 #include <linux/err.h>
 #include <linux/log2.h>
 #include <linux/math64.h>
-
-#include "analogbits-wrpll-cln28hpc.h"
+#include <linux/clk/analogbits-wrpll-cln28hpc.h>
 
 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
 #define MIN_INPUT_FREQ			7000000

+ 0 - 3
drivers/clk/sifive/Kconfig

@@ -1,8 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0
 
-config CLK_ANALOGBITS_WRPLL_CLN28HPC
-	bool
-
 config CLK_SIFIVE
 	bool "SiFive SoC driver support"
 	depends on CLK

+ 0 - 2
drivers/clk/sifive/Makefile

@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0+
 
-obj-$(CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC)	+= wrpll-cln28hpc.o
-
 obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI)		+= fu540-prci.o
 
 obj-$(CONFIG_CLK_SIFIVE_GEMGXL_MGMT)		+= gemgxl-mgmt.o

+ 1 - 2
drivers/clk/sifive/fu540-prci.c

@@ -37,10 +37,9 @@
 #include <errno.h>
 
 #include <linux/math64.h>
+#include <linux/clk/analogbits-wrpll-cln28hpc.h>
 #include <dt-bindings/clk/sifive-fu540-prci.h>
 
-#include "analogbits-wrpll-cln28hpc.h"
-
 /*
  * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
  *     hfclk and rtcclk

+ 0 - 0
drivers/clk/sifive/analogbits-wrpll-cln28hpc.h → include/linux/clk/analogbits-wrpll-cln28hpc.h