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@@ -0,0 +1,191 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Copyright 2019 Google LLC
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+ */
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+
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+#include <common.h>
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+#include <binman.h>
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+#include <binman_sym.h>
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+#include <cbfs.h>
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+#include <dm.h>
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+#include <init.h>
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+#include <spi.h>
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+#include <spl.h>
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+#include <spi_flash.h>
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+#include <asm/intel_pinctrl.h>
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+#include <dm/uclass-internal.h>
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+#include <asm/fsp2/fsp_internal.h>
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+
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+int arch_cpu_init_dm(void)
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+{
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+ struct udevice *dev;
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+ ofnode node;
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+ int ret;
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+
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+ /* Make sure pads are set up early in U-Boot */
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+ if (spl_phase() != PHASE_BOARD_F)
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+ return 0;
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+
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+ /* Probe all pinctrl devices to set up the pads */
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+ ret = uclass_first_device_err(UCLASS_PINCTRL, &dev);
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+ if (ret)
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+ return log_msg_ret("no fsp pinctrl", ret);
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+ node = ofnode_path("fsp");
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+ if (!ofnode_valid(node))
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+ return log_msg_ret("no fsp params", -EINVAL);
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+ ret = pinctrl_config_pads_for_node(dev, node);
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+ if (ret)
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+ return log_msg_ret("pad config", ret);
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+
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+ return ret;
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+}
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+
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+#if !defined(CONFIG_TPL_BUILD)
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+binman_sym_declare(ulong, intel_fsp_m, image_pos);
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+binman_sym_declare(ulong, intel_fsp_m, size);
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+
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+/**
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+ * get_cbfs_fsp() - Obtain the FSP by looking up in CBFS
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+ *
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+ * This looks up an FSP in a CBFS. It is used mostly for testing, when booting
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+ * U-Boot from a hybrid image containing coreboot as the first-stage bootloader.
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+ *
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+ * The typical use for this feature is when building a Chrome OS image which
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+ * includes coreboot in it. By adding U-Boot into the 'COREBOOT' CBFS as well,
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+ * it is possible to make coreboot chain-load U-Boot. Thus the initial stages of
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+ * the SoC init can be done by coreboot and the later stages by U-Boot. This is
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+ * a convenient way to start the porting work. The jump to U-Boot can then be
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+ * moved progressively earlier and earlier, until U-Boot takes over all the init
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+ * and you have a native port.
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+ *
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+ * This function looks up a CBFS at a known location and reads the FSP-M from it
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+ * so that U-Boot can init the memory.
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+ *
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+ * This function is not used in the normal boot but is kept here for future
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+ * development.
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+ *
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+ * @type; Type to look up (only FSP_M supported at present)
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+ * @map_base: Base memory address for mapped SPI
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+ * @entry: Returns an entry containing the position of the FSP image
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+ */
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+static int get_cbfs_fsp(enum fsp_type_t type, ulong map_base,
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+ struct binman_entry *entry)
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+{
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+ /*
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+ * Use a hard-coded position of CBFS in the ROM for now. It would be
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+ * possible to read the position using the FMAP in the ROM, but since
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+ * this code is only used for development, it doesn't seem worth it.
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+ * Use the 'cbfstool <image> layout' command to get these values, e.g.:
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+ * 'COREBOOT' (CBFS, size 1814528, offset 2117632).
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+ */
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+ ulong cbfs_base = 0x205000;
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+ ulong cbfs_size = 0x1bb000;
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+ struct cbfs_priv *cbfs;
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+ int ret;
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+
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+ ret = cbfs_init_mem(map_base + cbfs_base, cbfs_size, &cbfs);
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+ if (ret)
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+ return ret;
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+ if (!ret) {
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+ const struct cbfs_cachenode *node;
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+
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+ node = cbfs_find_file(cbfs, "fspm.bin");
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+ if (!node)
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+ return log_msg_ret("fspm node", -ENOENT);
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+
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+ entry->image_pos = (ulong)node->data;
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+ entry->size = node->data_length;
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+ }
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+
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+ return 0;
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+}
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+
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+int fsp_locate_fsp(enum fsp_type_t type, struct binman_entry *entry,
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+ bool use_spi_flash, struct udevice **devp,
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+ struct fsp_header **hdrp, ulong *rom_offsetp)
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+{
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+ ulong mask = CONFIG_ROM_SIZE - 1;
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+ struct udevice *dev;
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+ ulong rom_offset = 0;
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+ uint map_size;
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+ ulong map_base;
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+ uint offset;
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+ int ret;
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+
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+ /*
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+ * Find the devices but don't probe them, since we don't want to
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+ * auto-config PCI before silicon init runs
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+ */
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+ ret = uclass_find_first_device(UCLASS_NORTHBRIDGE, &dev);
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+ if (ret)
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+ return log_msg_ret("Cannot get northbridge", ret);
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+ if (!use_spi_flash) {
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+ struct udevice *sf;
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+
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+ /* Just use the SPI driver to get the memory map */
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+ ret = uclass_find_first_device(UCLASS_SPI_FLASH, &sf);
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+ if (ret)
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+ return log_msg_ret("Cannot get SPI flash", ret);
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+ ret = dm_spi_get_mmap(sf, &map_base, &map_size, &offset);
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+ if (ret)
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+ return log_msg_ret("Could not get flash mmap", ret);
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+ }
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+
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+ if (spl_phase() >= PHASE_BOARD_F) {
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+ if (type != FSP_S)
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+ return -EPROTONOSUPPORT;
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+ ret = binman_entry_find("intel-fsp-s", entry);
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+ if (ret)
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+ return log_msg_ret("binman entry", ret);
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+ if (!use_spi_flash)
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+ rom_offset = (map_base & mask) - CONFIG_ROM_SIZE;
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+ } else {
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+ ret = -ENOENT;
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+ if (false)
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+ /*
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+ * Support using a hybrid image build by coreboot. See
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+ * the function comments for details
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+ */
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+ ret = get_cbfs_fsp(type, map_base, entry);
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+ if (ret) {
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+ ulong mask = CONFIG_ROM_SIZE - 1;
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+
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+ if (type != FSP_M)
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+ return -EPROTONOSUPPORT;
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+ entry->image_pos = binman_sym(ulong, intel_fsp_m,
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+ image_pos);
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+ entry->size = binman_sym(ulong, intel_fsp_m, size);
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+ if (entry->image_pos != BINMAN_SYM_MISSING) {
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+ ret = 0;
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+ if (use_spi_flash)
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+ entry->image_pos &= mask;
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+ else
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+ entry->image_pos += (map_base & mask);
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+ } else {
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+ ret = -ENOENT;
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+ }
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+ }
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+ }
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+ if (ret)
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+ return log_msg_ret("Cannot find FSP", ret);
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+ entry->image_pos += rom_offset;
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+
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+ /*
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+ * Account for the time taken to read memory-mapped SPI flash since in
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+ * this case we don't use the SPI driver and BOOTSTAGE_ID_ACCUM_SPI.
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+ */
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+ if (!use_spi_flash)
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+ bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
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+ ret = fsp_get_header(entry->image_pos, entry->size, use_spi_flash,
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+ hdrp);
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+ if (!use_spi_flash)
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+ bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
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+ if (ret)
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+ return log_msg_ret("fsp_get_header", ret);
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+ *devp = dev;
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+ if (rom_offsetp)
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+ *rom_offsetp = rom_offset;
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+
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+ return 0;
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+}
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+#endif
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