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@@ -10,23 +10,20 @@
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#include <asm/arch/clock_manager.h>
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#include <wait_bit.h>
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-static const struct socfpga_clock_manager *clock_manager_base =
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- (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
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-
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/*
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* function to write the bypass register which requires a poll of the
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* busy bit
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*/
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static void cm_write_bypass(u32 val)
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{
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- writel(val, &clock_manager_base->bypass);
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+ writel(val, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_BYPASS);
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cm_wait_for_fsm();
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}
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/* function to write the ctrl register which requires a poll of the busy bit */
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static void cm_write_ctrl(u32 val)
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{
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- writel(val, &clock_manager_base->ctrl);
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+ writel(val, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_CTRL);
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cm_wait_for_fsm();
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}
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@@ -80,8 +77,8 @@ int cm_basic_init(const struct cm_config * const cfg)
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* gatting off the rest of the periperal clocks.
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*/
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writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
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- readl(&clock_manager_base->per_pll.en),
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- &clock_manager_base->per_pll.en);
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+ readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EN),
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EN);
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/* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
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writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
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@@ -90,12 +87,12 @@ int cm_basic_init(const struct cm_config * const cfg)
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CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
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CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
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CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
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- &clock_manager_base->main_pll.en);
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_EN);
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- writel(0, &clock_manager_base->sdr_pll.en);
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+ writel(0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_EN);
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/* now we can gate off the rest of the peripheral clocks */
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- writel(0, &clock_manager_base->per_pll.en);
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+ writel(0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EN);
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/* Put all plls in bypass */
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cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
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@@ -104,13 +101,13 @@ int cm_basic_init(const struct cm_config * const cfg)
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/* Put all plls VCO registers back to reset value. */
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writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
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~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
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- &clock_manager_base->main_pll.vco);
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
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writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
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~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
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- &clock_manager_base->per_pll.vco);
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
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writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
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~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
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- &clock_manager_base->sdr_pll.vco);
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
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/*
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* The clocks to the flash devices and the L4_MAIN clocks can
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@@ -120,23 +117,26 @@ int cm_basic_init(const struct cm_config * const cfg)
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* after exiting safe mode but before ungating the clocks.
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*/
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writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
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- &clock_manager_base->per_pll.src);
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_SRC);
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writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
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- &clock_manager_base->main_pll.l4src);
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_L4SRC);
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/* read back for the required 5 us delay. */
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- readl(&clock_manager_base->main_pll.vco);
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- readl(&clock_manager_base->per_pll.vco);
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- readl(&clock_manager_base->sdr_pll.vco);
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+ readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
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+ readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
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+ readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
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/*
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* We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
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* with numerator and denominator.
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*/
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- writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
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- writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
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- writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
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+ writel(cfg->main_vco_base,
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
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+ writel(cfg->peri_vco_base,
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
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+ writel(cfg->sdram_vco_base,
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
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/*
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* Time starts here. Must wait 7 us from
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@@ -145,44 +145,55 @@ int cm_basic_init(const struct cm_config * const cfg)
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end = timer_get_us() + 7;
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/* main mpu */
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- writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
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+ writel(cfg->mpuclk,
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MPUCLK);
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/* altera group mpuclk */
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- writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk);
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+ writel(cfg->altera_grp_mpuclk,
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_ALTR_MPUCLK);
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/* main main clock */
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- writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
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+ writel(cfg->mainclk,
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MAINCLK);
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/* main for dbg */
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- writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
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+ writel(cfg->dbgatclk,
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_DBGATCLK);
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/* main for cfgs2fuser0clk */
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writel(cfg->cfg2fuser0clk,
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- &clock_manager_base->main_pll.cfgs2fuser0clk);
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_CFGS2FUSER0CLK);
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/* Peri emac0 50 MHz default to RMII */
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- writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
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+ writel(cfg->emac0clk,
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EMAC0CLK);
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/* Peri emac1 50 MHz default to RMII */
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- writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
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+ writel(cfg->emac1clk,
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EMAC1CLK);
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/* Peri QSPI */
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- writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
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+ writel(cfg->mainqspiclk,
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MAINQSPICLK);
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- writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
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+ writel(cfg->perqspiclk,
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_PERQSPICLK);
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/* Peri pernandsdmmcclk */
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writel(cfg->mainnandsdmmcclk,
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- &clock_manager_base->main_pll.mainnandsdmmcclk);
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+ socfpga_get_clkmgr_addr() +
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+ CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK);
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writel(cfg->pernandsdmmcclk,
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- &clock_manager_base->per_pll.pernandsdmmcclk);
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK);
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/* Peri perbaseclk */
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- writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
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+ writel(cfg->perbaseclk,
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_PERBASECLK);
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/* Peri s2fuser1clk */
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- writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
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+ writel(cfg->s2fuser1clk,
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_S2FUSER1CLK);
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/* 7 us must have elapsed before we can enable the VCO */
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while (timer_get_us() < end)
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@@ -191,101 +202,112 @@ int cm_basic_init(const struct cm_config * const cfg)
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/* Enable vco */
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/* main pll vco */
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writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
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- &clock_manager_base->main_pll.vco);
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
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/* periferal pll */
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writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
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- &clock_manager_base->per_pll.vco);
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
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/* sdram pll vco */
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writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
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- &clock_manager_base->sdr_pll.vco);
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
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/* L3 MP and L3 SP */
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- writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
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+ writel(cfg->maindiv,
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MAINDIV);
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- writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
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+ writel(cfg->dbgdiv,
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_DBGDIV);
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- writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
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+ writel(cfg->tracediv,
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_TRACEDIV);
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/* L4 MP, L4 SP, can0, and can1 */
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- writel(cfg->perdiv, &clock_manager_base->per_pll.div);
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+ writel(cfg->perdiv,
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_DIV);
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- writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
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+ writel(cfg->gpiodiv,
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_GPIODIV);
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cm_wait_for_lock(LOCKED_MASK);
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/* write the sdram clock counters before toggling outreset all */
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writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
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- &clock_manager_base->sdr_pll.ddrdqsclk);
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDRDQSCLK);
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writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
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- &clock_manager_base->sdr_pll.ddr2xdqsclk);
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK);
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writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
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- &clock_manager_base->sdr_pll.ddrdqclk);
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDRDQCLK);
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writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
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- &clock_manager_base->sdr_pll.s2fuser2clk);
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_S2FUSER2CLK);
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/*
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* after locking, but before taking out of bypass
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* assert/deassert outresetall
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*/
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- u32 mainvco = readl(&clock_manager_base->main_pll.vco);
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+ u32 mainvco = readl(socfpga_get_clkmgr_addr() +
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+ CLKMGR_GEN5_MAINPLL_VCO);
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/* assert main outresetall */
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writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
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- &clock_manager_base->main_pll.vco);
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
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- u32 periphvco = readl(&clock_manager_base->per_pll.vco);
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+ u32 periphvco = readl(socfpga_get_clkmgr_addr() +
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+ CLKMGR_GEN5_PERPLL_VCO);
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/* assert pheriph outresetall */
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writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
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- &clock_manager_base->per_pll.vco);
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
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/* assert sdram outresetall */
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- writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
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- CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
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- &clock_manager_base->sdr_pll.vco);
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+ writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN |
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+ CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
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/* deassert main outresetall */
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writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
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- &clock_manager_base->main_pll.vco);
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
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/* deassert pheriph outresetall */
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writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
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- &clock_manager_base->per_pll.vco);
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
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/* deassert sdram outresetall */
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writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
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- &clock_manager_base->sdr_pll.vco);
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
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/*
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* now that we've toggled outreset all, all the clocks
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* are aligned nicely; so we can change any phase.
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*/
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ret = cm_write_with_phase(cfg->ddrdqsclk,
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- &clock_manager_base->sdr_pll.ddrdqsclk,
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+ (const void *)(socfpga_get_clkmgr_addr() +
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+ CLKMGR_GEN5_SDRPLL_DDRDQSCLK),
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CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
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if (ret)
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return ret;
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/* SDRAM DDR2XDQSCLK */
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ret = cm_write_with_phase(cfg->ddr2xdqsclk,
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- &clock_manager_base->sdr_pll.ddr2xdqsclk,
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+ (const void *)(socfpga_get_clkmgr_addr() +
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+ CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK),
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CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
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if (ret)
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return ret;
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ret = cm_write_with_phase(cfg->ddrdqclk,
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- &clock_manager_base->sdr_pll.ddrdqclk,
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+ (const void *)(socfpga_get_clkmgr_addr() +
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+ CLKMGR_GEN5_SDRPLL_DDRDQCLK),
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CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
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if (ret)
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return ret;
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ret = cm_write_with_phase(cfg->s2fuser2clk,
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- &clock_manager_base->sdr_pll.s2fuser2clk,
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+ (const void *)(socfpga_get_clkmgr_addr() +
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+ CLKMGR_GEN5_SDRPLL_S2FUSER2CLK),
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CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
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if (ret)
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return ret;
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@@ -294,24 +316,28 @@ int cm_basic_init(const struct cm_config * const cfg)
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cm_write_bypass(0);
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/* clear safe mode */
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- cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
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+ cm_write_ctrl(readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_CTRL) |
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+ CLKMGR_CTRL_SAFEMODE);
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/*
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* now that safe mode is clear with clocks gated
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|
* it safe to change the source mux for the flashes the the L4_MAIN
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*/
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- writel(cfg->persrc, &clock_manager_base->per_pll.src);
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- writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
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+ writel(cfg->persrc,
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_SRC);
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+ writel(cfg->l4src,
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_L4SRC);
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|
/* Now ungate non-hw-managed clocks */
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|
- writel(~0, &clock_manager_base->main_pll.en);
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- writel(~0, &clock_manager_base->per_pll.en);
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- writel(~0, &clock_manager_base->sdr_pll.en);
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+ writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_EN);
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+ writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_EN);
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+ writel(~0, socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_EN);
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|
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/* Clear the loss of lock bits (write 1 to clear) */
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- writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK |
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- CLKMGR_INTER_MAINPLLLOST_MASK,
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- &clock_manager_base->inter);
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+ writel(CLKMGR_INTER_SDRPLLLOST_MASK |
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+ CLKMGR_INTER_PERPLLLOST_MASK |
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+ CLKMGR_INTER_MAINPLLLOST_MASK,
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|
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+ socfpga_get_clkmgr_addr() + CLKMGR_GEN5_INTER);
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return 0;
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}
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@@ -321,7 +347,7 @@ static unsigned int cm_get_main_vco_clk_hz(void)
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u32 reg, clock;
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/* get the main VCO clock */
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- reg = readl(&clock_manager_base->main_pll.vco);
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+ reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
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clock = cm_get_osc_clk_hz(1);
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clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
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CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
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@@ -336,7 +362,7 @@ static unsigned int cm_get_per_vco_clk_hz(void)
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u32 reg, clock = 0;
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|
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/* identify PER PLL clock source */
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- reg = readl(&clock_manager_base->per_pll.vco);
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+ reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
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|
reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
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|
CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
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if (reg == CLKMGR_VCO_SSRC_EOSC1)
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|
@@ -347,7 +373,7 @@ static unsigned int cm_get_per_vco_clk_hz(void)
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|
clock = cm_get_f2s_per_ref_clk_hz();
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|
|
|
|
/* get the PER VCO clock */
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- reg = readl(&clock_manager_base->per_pll.vco);
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|
+ reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
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|
clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
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|
|
CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
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|
clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
|
|
@@ -363,9 +389,9 @@ unsigned long cm_get_mpu_clk_hz(void)
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|
clock = cm_get_main_vco_clk_hz();
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|
|
|
|
|
/* get the MPU clock */
|
|
|
- reg = readl(&clock_manager_base->altera.mpuclk);
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|
|
+ reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_ALTR_MPUCLK);
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|
|
clock /= (reg + 1);
|
|
|
- reg = readl(&clock_manager_base->main_pll.mpuclk);
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|
|
+ reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MPUCLK);
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|
|
clock /= (reg + 1);
|
|
|
return clock;
|
|
|
}
|
|
@@ -375,7 +401,7 @@ unsigned long cm_get_sdram_clk_hz(void)
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|
|
u32 reg, clock = 0;
|
|
|
|
|
|
/* identify SDRAM PLL clock source */
|
|
|
- reg = readl(&clock_manager_base->sdr_pll.vco);
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|
|
+ reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
|
|
|
reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
|
|
|
CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
|
|
|
if (reg == CLKMGR_VCO_SSRC_EOSC1)
|
|
@@ -386,14 +412,14 @@ unsigned long cm_get_sdram_clk_hz(void)
|
|
|
clock = cm_get_f2s_sdr_ref_clk_hz();
|
|
|
|
|
|
/* get the SDRAM VCO clock */
|
|
|
- reg = readl(&clock_manager_base->sdr_pll.vco);
|
|
|
+ reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_VCO);
|
|
|
clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
|
|
|
CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
|
|
|
clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
|
|
|
CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
|
|
|
|
|
|
/* get the SDRAM (DDR_DQS) clock */
|
|
|
- reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
|
|
|
+ reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_SDRPLL_DDRDQSCLK);
|
|
|
reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
|
|
|
CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
|
|
|
clock /= (reg + 1);
|
|
@@ -406,7 +432,7 @@ unsigned int cm_get_l4_sp_clk_hz(void)
|
|
|
u32 reg, clock = 0;
|
|
|
|
|
|
/* identify the source of L4 SP clock */
|
|
|
- reg = readl(&clock_manager_base->main_pll.l4src);
|
|
|
+ reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_L4SRC);
|
|
|
reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
|
|
|
CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
|
|
|
|
|
@@ -414,20 +440,23 @@ unsigned int cm_get_l4_sp_clk_hz(void)
|
|
|
clock = cm_get_main_vco_clk_hz();
|
|
|
|
|
|
/* get the clock prior L4 SP divider (main clk) */
|
|
|
- reg = readl(&clock_manager_base->altera.mainclk);
|
|
|
+ reg = readl(socfpga_get_clkmgr_addr() +
|
|
|
+ CLKMGR_GEN5_ALTR_MAINCLK);
|
|
|
clock /= (reg + 1);
|
|
|
- reg = readl(&clock_manager_base->main_pll.mainclk);
|
|
|
+ reg = readl(socfpga_get_clkmgr_addr() +
|
|
|
+ CLKMGR_GEN5_MAINPLL_MAINCLK);
|
|
|
clock /= (reg + 1);
|
|
|
} else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
|
|
|
clock = cm_get_per_vco_clk_hz();
|
|
|
|
|
|
/* get the clock prior L4 SP divider (periph_base_clk) */
|
|
|
- reg = readl(&clock_manager_base->per_pll.perbaseclk);
|
|
|
+ reg = readl(socfpga_get_clkmgr_addr() +
|
|
|
+ CLKMGR_GEN5_PERPLL_PERBASECLK);
|
|
|
clock /= (reg + 1);
|
|
|
}
|
|
|
|
|
|
/* get the L4 SP clock which supplied to UART */
|
|
|
- reg = readl(&clock_manager_base->main_pll.maindiv);
|
|
|
+ reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_MAINDIV);
|
|
|
reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
|
|
|
CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
|
|
|
clock = clock / (1 << reg);
|
|
@@ -440,7 +469,7 @@ unsigned int cm_get_mmc_controller_clk_hz(void)
|
|
|
u32 reg, clock = 0;
|
|
|
|
|
|
/* identify the source of MMC clock */
|
|
|
- reg = readl(&clock_manager_base->per_pll.src);
|
|
|
+ reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_SRC);
|
|
|
reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
|
|
|
CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
|
|
|
|
|
@@ -450,13 +479,15 @@ unsigned int cm_get_mmc_controller_clk_hz(void)
|
|
|
clock = cm_get_main_vco_clk_hz();
|
|
|
|
|
|
/* get the SDMMC clock */
|
|
|
- reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
|
|
|
+ reg = readl(socfpga_get_clkmgr_addr() +
|
|
|
+ CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK);
|
|
|
clock /= (reg + 1);
|
|
|
} else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
|
|
|
clock = cm_get_per_vco_clk_hz();
|
|
|
|
|
|
/* get the SDMMC clock */
|
|
|
- reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
|
|
|
+ reg = readl(socfpga_get_clkmgr_addr() +
|
|
|
+ CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK);
|
|
|
clock /= (reg + 1);
|
|
|
}
|
|
|
|
|
@@ -470,7 +501,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
|
|
|
u32 reg, clock = 0;
|
|
|
|
|
|
/* identify the source of QSPI clock */
|
|
|
- reg = readl(&clock_manager_base->per_pll.src);
|
|
|
+ reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_SRC);
|
|
|
reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
|
|
|
CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
|
|
|
|
|
@@ -480,13 +511,15 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
|
|
|
clock = cm_get_main_vco_clk_hz();
|
|
|
|
|
|
/* get the qspi clock */
|
|
|
- reg = readl(&clock_manager_base->main_pll.mainqspiclk);
|
|
|
+ reg = readl(socfpga_get_clkmgr_addr() +
|
|
|
+ CLKMGR_GEN5_MAINPLL_MAINQSPICLK);
|
|
|
clock /= (reg + 1);
|
|
|
} else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
|
|
|
clock = cm_get_per_vco_clk_hz();
|
|
|
|
|
|
/* get the qspi clock */
|
|
|
- reg = readl(&clock_manager_base->per_pll.perqspiclk);
|
|
|
+ reg = readl(socfpga_get_clkmgr_addr() +
|
|
|
+ CLKMGR_GEN5_PERPLL_PERQSPICLK);
|
|
|
clock /= (reg + 1);
|
|
|
}
|
|
|
|
|
@@ -500,7 +533,7 @@ unsigned int cm_get_spi_controller_clk_hz(void)
|
|
|
clock = cm_get_per_vco_clk_hz();
|
|
|
|
|
|
/* get the clock prior L4 SP divider (periph_base_clk) */
|
|
|
- reg = readl(&clock_manager_base->per_pll.perbaseclk);
|
|
|
+ reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_PERBASECLK);
|
|
|
clock /= (reg + 1);
|
|
|
|
|
|
return clock;
|