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imx: rename mx8m,MX8M to imx8m,IMX8M

Rename mx8m,MX8M to imx8m,IMX8M

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jon Nettleton <jon@solid-run.com>
Peng Fan %!s(int64=5) %!d(string=hai) anos
pai
achega
cd357ad112

+ 2 - 2
arch/arm/Kconfig

@@ -694,7 +694,7 @@ config ARCH_IMX8
 	select DM
 	select OF_CONTROL
 
-config ARCH_MX8M
+config ARCH_IMX8M
 	bool "NXP i.MX8M platform"
 	select ARM64
 	select DM
@@ -1451,7 +1451,7 @@ source "arch/arm/mach-imx/mx7ulp/Kconfig"
 
 source "arch/arm/mach-imx/imx8/Kconfig"
 
-source "arch/arm/mach-imx/mx8m/Kconfig"
+source "arch/arm/mach-imx/imx8m/Kconfig"
 
 source "arch/arm/mach-imx/mxs/Kconfig"
 

+ 2 - 2
arch/arm/Makefile

@@ -103,11 +103,11 @@ libs-y += arch/arm/cpu/
 libs-y += arch/arm/lib/
 
 ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 mx8m))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m))
 libs-y += arch/arm/mach-imx/
 endif
 else
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs mx8m imx8 vf610))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 vf610))
 libs-y += arch/arm/mach-imx/
 endif
 endif

+ 2 - 2
arch/arm/include/asm/arch-imx/cpu.h

@@ -24,7 +24,7 @@
 #define MXC_CPU_MX6QP		0x69
 #define MXC_CPU_MX7S		0x71 /* dummy ID */
 #define MXC_CPU_MX7D		0x72
-#define MXC_CPU_MX8MQ		0x82
+#define MXC_CPU_IMX8MQ		0x82
 #define MXC_CPU_IMX8QXP_A0	0x90 /* dummy ID */
 #define MXC_CPU_IMX8QXP		0x92 /* dummy ID */
 #define MXC_CPU_MX7ULP		0xE1 /* Temporally hard code */
@@ -32,7 +32,7 @@
 
 #define MXC_SOC_MX6		0x60
 #define MXC_SOC_MX7		0x70
-#define MXC_SOC_MX8M		0x80
+#define MXC_SOC_IMX8M		0x80
 #define MXC_SOC_IMX8		0x90 /* dummy */
 #define MXC_SOC_MX7ULP		0xE0 /* dummy */
 

+ 0 - 0
arch/arm/include/asm/arch-mx8m/clock.h → arch/arm/include/asm/arch-imx8m/clock.h


+ 2 - 2
arch/arm/include/asm/arch-mx8m/crm_regs.h → arch/arm/include/asm/arch-imx8m/crm_regs.h

@@ -3,7 +3,7 @@
  * Copyright 2017 NXP
  */
 
-#ifndef _ASM_ARCH_MX8M_CRM_REGS_H
-#define _ASM_ARCH_MX8M_CRM_REGS_H
+#ifndef _ASM_ARCH_IMX8M_CRM_REGS_H
+#define _ASM_ARCH_IMX8M_CRM_REGS_H
 /* Dummy header, some imx-common code needs this file */
 #endif

+ 2 - 2
arch/arm/include/asm/arch-mx8m/ddr.h → arch/arm/include/asm/arch-imx8m/ddr.h

@@ -3,8 +3,8 @@
  * Copyright 2017 NXP
  */
 
-#ifndef __ASM_ARCH_MX8M_DDR_H
-#define __ASM_ARCH_MX8M_DDR_H
+#ifndef __ASM_ARCH_IMX8M_DDR_H
+#define __ASM_ARCH_IMX8M_DDR_H
 
 #define DDRC_DDR_SS_GPR0		0x3d000000
 #define DDRC_IPS_BASE_ADDR_0		0x3f400000

+ 2 - 2
arch/arm/include/asm/arch-mx8m/gpio.h → arch/arm/include/asm/arch-imx8m/gpio.h

@@ -3,8 +3,8 @@
  * Copyright 2017 NXP
  */
 
-#ifndef __ASM_ARCH_MX8M_GPIO_H
-#define __ASM_ARCH_MX8M_GPIO_H
+#ifndef __ASM_ARCH_IMX8M_GPIO_H
+#define __ASM_ARCH_IMX8M_GPIO_H
 
 #include <asm/mach-imx/gpio.h>
 

+ 2 - 2
arch/arm/include/asm/arch-mx8m/imx-regs.h → arch/arm/include/asm/arch-imx8m/imx-regs.h

@@ -3,8 +3,8 @@
  * Copyright 2017 NXP
  */
 
-#ifndef __ASM_ARCH_MX8M_REGS_H__
-#define __ASM_ARCH_MX8M_REGS_H__
+#ifndef __ASM_ARCH_IMX8M_REGS_H__
+#define __ASM_ARCH_IMX8M_REGS_H__
 
 #include <asm/mach-imx/regs-lcdif.h>
 

+ 2 - 2
arch/arm/include/asm/arch-mx8m/mx8mq_pins.h → arch/arm/include/asm/arch-imx8m/imx8mq_pins.h

@@ -3,8 +3,8 @@
  * Copyright (C) 2017 NXP
  */
 
-#ifndef __ASM_ARCH_MX8MQ_PINS_H__
-#define __ASM_ARCH_MX8MQ_PINS_H__
+#ifndef __ASM_ARCH_IMX8MQ_PINS_H__
+#define __ASM_ARCH_IMX8MQ_PINS_H__
 
 #include <asm/mach-imx/iomux-v3.h>
 

+ 2 - 2
arch/arm/include/asm/arch-mx8m/sys_proto.h → arch/arm/include/asm/arch-imx8m/sys_proto.h

@@ -3,8 +3,8 @@
  * Copyright (C) 2017 NXP
  */
 
-#ifndef __ARCH_MX8M_SYS_PROTO_H
-#define __ARCH_MX8M_SYS_PROTO_H
+#ifndef __ARCH_IMX8M_SYS_PROTO_H
+#define __ARCH_NMX8M_SYS_PROTO_H
 
 #include <asm/mach-imx/sys_proto.h>
 

+ 1 - 1
arch/arm/include/asm/mach-imx/iomux-v3.h

@@ -86,7 +86,7 @@ typedef u64 iomux_v3_cfg_t;
 #define IOMUX_CONFIG_LPSR       0x20
 #define MUX_MODE_LPSR           ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
 				MUX_MODE_SHIFT)
-#ifdef CONFIG_MX8M
+#ifdef CONFIG_IMX8M
 #define PAD_CTL_DSE0		(0x0 << 0)
 #define PAD_CTL_DSE1		(0x1 << 0)
 #define PAD_CTL_DSE2		(0x2 << 0)

+ 3 - 3
arch/arm/include/asm/mach-imx/regs-lcdif.h

@@ -22,7 +22,7 @@ struct mxs_lcdif_regs {
 	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
 	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
 	defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
-	defined(CONFIG_MX8M)
+	defined(CONFIG_IMX8M)
 	mxs_reg_32(hw_lcdif_ctrl2)		/* 0x20 */
 #endif
 	mxs_reg_32(hw_lcdif_transfer_count)	/* 0x20/0x30 */
@@ -61,7 +61,7 @@ struct mxs_lcdif_regs {
 	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
 	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
 	defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
-	defined(CONFIG_MX8M)
+	defined(CONFIG_IMX8M)
 	mxs_reg_32(hw_lcdif_crc_stat)		/* 0x1a0 */
 #endif
 	mxs_reg_32(hw_lcdif_lcdif_stat)		/* 0x1d0/0x1b0 */
@@ -73,7 +73,7 @@ struct mxs_lcdif_regs {
 	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
 	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
 	defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
-	defined(CONFIG_MX8M)
+	defined(CONFIG_IMX8M)
 	mxs_reg_32(hw_lcdif_thres)
 	mxs_reg_32(hw_lcdif_as_ctrl)
 	mxs_reg_32(hw_lcdif_as_buf)

+ 1 - 1
arch/arm/include/asm/mach-imx/sys_proto.h

@@ -26,7 +26,7 @@
 
 #define is_mx6() (is_soc_type(MXC_SOC_MX6))
 #define is_mx7() (is_soc_type(MXC_SOC_MX7))
-#define is_mx8m() (is_soc_type(MXC_SOC_MX8M))
+#define is_imx8m() (is_soc_type(MXC_SOC_IMX8M))
 #define is_imx8() (is_soc_type(MXC_SOC_IMX8))
 
 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))

+ 4 - 4
arch/arm/mach-imx/Makefile

@@ -5,11 +5,11 @@
 #
 # (C) Copyright 2011 Freescale Semiconductor, Inc.
 
-ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 mx8m vf610))
+ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 imx8m vf610))
 obj-y	= iomux-v3.o
 endif
 
-ifeq ($(SOC),$(filter $(SOC),mx8m))
+ifeq ($(SOC),$(filter $(SOC),imx8m))
 obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
 obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
 obj-$(CONFIG_FEC_MXC) += mac.o
@@ -22,7 +22,7 @@ obj-y	+= cpu.o speed.o
 obj-$(CONFIG_GPT_TIMER) += timer.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 endif
-ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx8m))
+ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m))
 obj-y	+= misc.o
 obj-$(CONFIG_SPL_BUILD)	+= spl.o
 endif
@@ -169,5 +169,5 @@ obj-$(CONFIG_MX5) += mx5/
 obj-$(CONFIG_MX6) += mx6/
 obj-$(CONFIG_MX7) += mx7/
 obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
-obj-$(CONFIG_MX8M) += mx8m/
+obj-$(CONFIG_IMX8M) += imx8m/
 obj-$(CONFIG_ARCH_IMX8) += imx8/

+ 8 - 8
arch/arm/mach-imx/cpu.c

@@ -62,7 +62,7 @@ static char *get_reset_cause(void)
 		return "WDOG4";
 	case 0x00200:
 		return "TEMPSENSE";
-#elif defined(CONFIG_MX8M)
+#elif defined(CONFIG_IMX8M)
 	case 0x00100:
 		return "WDOG2";
 	case 0x00200:
@@ -142,8 +142,8 @@ unsigned imx_ddr_size(void)
 const char *get_imx_type(u32 imxtype)
 {
 	switch (imxtype) {
-	case MXC_CPU_MX8MQ:
-		return "8MQ";	/* Quad-core version of the mx8m */
+	case MXC_CPU_IMX8MQ:
+		return "8MQ";	/* Quad-core version of the imx8m */
 	case MXC_CPU_MX7S:
 		return "7S";	/* Single-core version of the mx7 */
 	case MXC_CPU_MX7D:
@@ -266,7 +266,7 @@ int cpu_mmc_init(bd_t *bis)
 }
 #endif
 
-#if !(defined(CONFIG_MX7) || defined(CONFIG_MX8M))
+#if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
 u32 get_ahb_clk(void)
 {
 	struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -300,7 +300,7 @@ void arch_preboot_os(void)
 #endif
 }
 
-#ifndef CONFIG_MX8M
+#ifndef CONFIG_IMX8M
 void set_chipselect_size(int const cs_size)
 {
 	unsigned int reg;
@@ -333,7 +333,7 @@ void set_chipselect_size(int const cs_size)
 }
 #endif
 
-#if defined(CONFIG_MX7) || defined(CONFIG_MX8M)
+#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
 /*
  * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
  * defines a 2-bit SPEED_GRADING
@@ -409,7 +409,7 @@ u32 get_cpu_temp_grade(int *minc, int *maxc)
 }
 #endif
 
-#if defined(CONFIG_MX7) || defined(CONFIG_MX8M)
+#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
 enum boot_device get_boot_device(void)
 {
 	struct bootrom_sw_info **p =
@@ -438,7 +438,7 @@ enum boot_device get_boot_device(void)
 	case BOOT_TYPE_SPINOR:
 		boot_dev = SPI_NOR_BOOT;
 		break;
-#ifdef CONFIG_MX8M
+#ifdef CONFIG_IMX8M
 	case BOOT_TYPE_USB:
 		boot_dev = USB_BOOT;
 		break;

+ 3 - 3
arch/arm/mach-imx/mx8m/Kconfig → arch/arm/mach-imx/imx8m/Kconfig

@@ -1,10 +1,10 @@
-if ARCH_MX8M
+if ARCH_IMX8M
 
-config MX8M
+config IMX8M
 	bool
 	select ROM_UNIFIED_SECTIONS
 
 config SYS_SOC
-	default "mx8m"
+	default "imx8m"
 
 endif

+ 0 - 0
arch/arm/mach-imx/mx8m/Makefile → arch/arm/mach-imx/imx8m/Makefile


+ 2 - 2
arch/arm/mach-imx/mx8m/clock.c → arch/arm/mach-imx/imx8m/clock.c

@@ -730,7 +730,7 @@ int clock_init(void)
  * Dump some clockes.
  */
 #ifndef CONFIG_SPL_BUILD
-int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
+int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
 		       char * const argv[])
 {
 	u32 freq;
@@ -785,7 +785,7 @@ int do_mx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
 }
 
 U_BOOT_CMD(
-	clocks,	CONFIG_SYS_MAXARGS, 1, do_mx8m_showclocks,
+	clocks,	CONFIG_SYS_MAXARGS, 1, do_imx8m_showclocks,
 	"display clocks",
 	""
 );

+ 0 - 0
arch/arm/mach-imx/mx8m/clock_slice.c → arch/arm/mach-imx/imx8m/clock_slice.c


+ 0 - 0
arch/arm/mach-imx/mx8m/lowlevel_init.S → arch/arm/mach-imx/imx8m/lowlevel_init.S


+ 0 - 0
arch/arm/mach-imx/mx8m/soc.c → arch/arm/mach-imx/imx8m/soc.c


+ 2 - 2
arch/arm/mach-imx/imx_bootaux.c

@@ -25,7 +25,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
 	writel(pc, M4_BOOTROM_BASE_ADDR + 4);
 
 	/* Enable M4 */
-#ifdef CONFIG_MX8M
+#ifdef CONFIG_IMX8M
 	call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0);
 #else
 	clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
@@ -37,7 +37,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
 
 int arch_auxiliary_core_check_up(u32 core_id)
 {
-#ifdef CONFIG_MX8M
+#ifdef CONFIG_IMX8M
 	return call_imx_sip(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0);
 #else
 	unsigned int val;

+ 3 - 3
arch/arm/mach-imx/spl.c

@@ -96,8 +96,8 @@ u32 spl_boot_device(void)
 	return BOOT_DEVICE_NONE;
 }
 
-#elif defined(CONFIG_MX7) || defined(CONFIG_MX8M)
-/* Translate iMX7/MX8M boot device to the SPL boot device enumeration */
+#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
+/* Translate iMX7/i.MX8M boot device to the SPL boot device enumeration */
 u32 spl_boot_device(void)
 {
 #if defined(CONFIG_MX7)
@@ -143,7 +143,7 @@ u32 spl_boot_device(void)
 		return BOOT_DEVICE_NONE;
 	}
 }
-#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_MX8M */
+#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_IMX8M */
 
 #ifdef CONFIG_SPL_USB_GADGET_SUPPORT
 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)

+ 9 - 9
drivers/gpio/mxc_gpio.c

@@ -40,15 +40,15 @@ static unsigned long gpio_ports[] = {
 	[2] = GPIO3_BASE_ADDR,
 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
 		defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
-		defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \
+		defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
 		defined(CONFIG_ARCH_IMX8)
 	[3] = GPIO4_BASE_ADDR,
 #endif
 #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
-		defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \
+		defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
 		defined(CONFIG_ARCH_IMX8)
 	[4] = GPIO5_BASE_ADDR,
-#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX8M))
+#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_IMX8M))
 	[5] = GPIO6_BASE_ADDR,
 #endif
 #endif
@@ -353,13 +353,13 @@ static const struct mxc_gpio_plat mxc_plat[] = {
 	{ 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
 		defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
-		defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8)
+		defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
 	{ 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
 #endif
 #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
-		defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8)
+		defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
 	{ 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
-#ifndef CONFIG_MX8M
+#ifndef CONFIG_IMX8M
 	{ 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
 #endif
 #endif
@@ -377,13 +377,13 @@ U_BOOT_DEVICES(mxc_gpios) = {
 	{ "gpio_mxc", &mxc_plat[2] },
 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
 		defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
-		defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8)
+		defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
 	{ "gpio_mxc", &mxc_plat[3] },
 #endif
 #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
-		defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8)
+		defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
 	{ "gpio_mxc", &mxc_plat[4] },
-#ifndef CONFIG_MX8M
+#ifndef CONFIG_IMX8M
 	{ "gpio_mxc", &mxc_plat[5] },
 #endif
 #endif

+ 3 - 3
drivers/misc/mxc_ocotp.c

@@ -34,7 +34,7 @@
 #define BM_OUT_STATUS_DED				0x00000400
 #define BM_OUT_STATUS_LOCKED			0x00000800
 #define BM_OUT_STATUS_PROGFAIL			0x00001000
-#elif defined(CONFIG_MX8M)
+#elif defined(CONFIG_IMX8M)
 #define BM_CTRL_ADDR			0x000000ff
 #else
 #define BM_CTRL_ADDR			0x0000007f
@@ -80,7 +80,7 @@
 #elif defined(CONFIG_MX7ULP)
 #define FUSE_BANK_SIZE	0x80
 #define FUSE_BANKS	31
-#elif defined(CONFIG_MX8M)
+#elif defined(CONFIG_IMX8M)
 #define FUSE_BANK_SIZE	0x40
 #define FUSE_BANKS	64
 #else
@@ -298,7 +298,7 @@ static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
 	u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
 #ifdef CONFIG_MX7
 	u32 addr = bank;
-#elif defined CONFIG_MX8M
+#elif defined CONFIG_IMX8M
 	u32 addr = bank << 2 | word;
 #else
 	u32 addr;

+ 4 - 4
drivers/mmc/fsl_esdhc.c

@@ -259,7 +259,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
 	int timeout;
 	struct fsl_esdhc *regs = priv->esdhc_regs;
 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
-	defined(CONFIG_IMX8) || defined(CONFIG_MX8M)
+	defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
 	dma_addr_t addr;
 #endif
 	uint wml_value;
@@ -273,7 +273,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
 		esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
-	defined(CONFIG_IMX8) || defined(CONFIG_MX8M)
+	defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
 		addr = virt_to_phys((void *)(data->dest));
 		if (upper_32_bits(addr))
 			printf("Error found for upper 32 bits\n");
@@ -303,7 +303,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
 					wml_value << 16);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
-	defined(CONFIG_IMX8) || defined(CONFIG_MX8M)
+	defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
 		addr = virt_to_phys((void *)(data->src));
 		if (upper_32_bits(addr))
 			printf("Error found for upper 32 bits\n");
@@ -369,7 +369,7 @@ static void check_and_invalidate_dcache_range
 	unsigned size = roundup(ARCH_DMA_MINALIGN,
 				data->blocks*data->blocksize);
 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
-	defined(CONFIG_IMX8) || defined(CONFIG_MX8M)
+	defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
 	dma_addr_t addr;
 
 	addr = virt_to_phys((void *)(data->dest));

+ 1 - 1
drivers/net/fec_mxc.c

@@ -604,7 +604,7 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
 	writel(0x00000000, &fec->eth->gaddr2);
 
 	/* Do not access reserved register */
-	if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) {
+	if (!is_mx6ul() && !is_mx6ull() && !is_imx8m()) {
 		/* clear MIB RAM */
 		for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
 			writel(0, i);