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@@ -58,7 +58,7 @@
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* All newly added entries should describe *hardware* and should use SECT_4K
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* (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
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* scenarios excluding small sectors there is config option that can be
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- * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
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+ * disabled: CONFIG_SPI_FLASH_USE_4K_SECTORS.
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* For historical (and compatibility) reasons (before we got above config) some
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* old entries may be missing 4K flag.
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*/
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@@ -75,6 +75,7 @@ const struct flash_info spi_nor_ids[] = {
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{ INFO("at45db161d", 0x1f2600, 0, 64 * 1024, 32, SECT_4K) },
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{ INFO("at45db321d", 0x1f2700, 0, 64 * 1024, 64, SECT_4K) },
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{ INFO("at45db641d", 0x1f2800, 0, 64 * 1024, 128, SECT_4K) },
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+ { INFO("at25sl321", 0x1f4216, 0, 64 * 1024, 64, SECT_4K) },
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{ INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
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#endif
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#ifdef CONFIG_SPI_FLASH_EON /* EON */
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@@ -128,6 +129,8 @@ const struct flash_info spi_nor_ids[] = {
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ INFO("is25wp128", 0x9d7018, 0, 64 * 1024, 256,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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+ { INFO("is25wp256", 0x9d7019, 0, 64 * 1024, 512,
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+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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#endif
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#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
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/* Macronix */
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@@ -161,12 +164,16 @@ const struct flash_info spi_nor_ids[] = {
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{ INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
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{ INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
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{ INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
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- { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
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- { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
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+ { INFO6("mt25ql256a", 0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
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+ { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR) },
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+ { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
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+ { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) },
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{ INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024,
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- SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
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- { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
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- { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
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+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
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+ USE_FSR) },
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+ { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
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+ { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
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+ { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
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{ INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
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{ INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
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{ INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
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