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@@ -38,6 +38,16 @@
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enable-method = "psci";
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};
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+ a53_1: cpu@1 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a53", "arm,armv8";
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+ reg = <1>;
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+ clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
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+ power-domains = <&sysc R8A77970_PD_CA53_CPU1>;
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+ next-level-cache = <&L2_CA53>;
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+ enable-method = "psci";
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+ };
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+
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L2_CA53: cache-controller {
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compatible = "cache";
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power-domains = <&sysc R8A77970_PD_CA53_SCU>;
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@@ -60,11 +70,25 @@
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clock-frequency = <0>;
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};
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+ pmu_a53 {
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+ compatible = "arm,cortex-a53-pmu";
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+ interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
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+ <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-affinity = <&a53_0>, <&a53_1>;
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+ };
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+
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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+ /* External CAN clock - to be overridden by boards that provide it */
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+ can_clk: can {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <0>;
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+ };
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+
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/* External SCIF clock - to be overridden by boards that provide it */
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scif_clk: scif {
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compatible = "fixed-clock";
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@@ -80,23 +104,6 @@
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#size-cells = <2>;
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ranges;
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- gic: interrupt-controller@f1010000 {
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- compatible = "arm,gic-400";
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- #interrupt-cells = <3>;
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- #address-cells = <0>;
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- interrupt-controller;
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- reg = <0 0xf1010000 0 0x1000>,
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- <0 0xf1020000 0 0x20000>,
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- <0 0xf1040000 0 0x20000>,
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- <0 0xf1060000 0 0x20000>;
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- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
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- IRQ_TYPE_LEVEL_HIGH)>;
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- clocks = <&cpg CPG_MOD 408>;
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- clock-names = "clk";
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- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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- resets = <&cpg 408>;
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- };
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-
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rwdt: watchdog@e6020000 {
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compatible = "renesas,r8a77970-wdt",
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"renesas,rcar-gen3-wdt";
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@@ -107,75 +114,6 @@
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status = "disabled";
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};
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- cpg: clock-controller@e6150000 {
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- compatible = "renesas,r8a77970-cpg-mssr";
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- reg = <0 0xe6150000 0 0x1000>;
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- clocks = <&extal_clk>, <&extalr_clk>;
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- clock-names = "extal", "extalr";
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- #clock-cells = <2>;
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- #power-domain-cells = <0>;
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- #reset-cells = <1>;
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- };
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-
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- rst: reset-controller@e6160000 {
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- compatible = "renesas,r8a77970-rst";
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- reg = <0 0xe6160000 0 0x200>;
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- };
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-
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- sysc: system-controller@e6180000 {
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- compatible = "renesas,r8a77970-sysc";
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- reg = <0 0xe6180000 0 0x440>;
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- #power-domain-cells = <1>;
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- };
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-
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- ipmmu_vi0: mmu@febd0000 {
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- compatible = "renesas,ipmmu-r8a77970";
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- reg = <0 0xfebd0000 0 0x1000>;
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- renesas,ipmmu-main = <&ipmmu_mm 9>;
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- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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- #iommu-cells = <1>;
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- status = "disabled";
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- };
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-
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- ipmmu_ir: mmu@ff8b0000 {
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- compatible = "renesas,ipmmu-r8a77970";
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- reg = <0 0xff8b0000 0 0x1000>;
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- renesas,ipmmu-main = <&ipmmu_mm 3>;
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- power-domains = <&sysc R8A77970_PD_A3IR>;
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- #iommu-cells = <1>;
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- status = "disabled";
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- };
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-
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- ipmmu_rt: mmu@ffc80000 {
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- compatible = "renesas,ipmmu-r8a77970";
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- reg = <0 0xffc80000 0 0x1000>;
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- renesas,ipmmu-main = <&ipmmu_mm 7>;
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- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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- #iommu-cells = <1>;
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- };
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-
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- ipmmu_ds1: mmu@e7740000 {
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- compatible = "renesas,ipmmu-r8a77970";
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- reg = <0 0xe7740000 0 0x1000>;
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- renesas,ipmmu-main = <&ipmmu_mm 1>;
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- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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- #iommu-cells = <1>;
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- };
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-
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- ipmmu_mm: mmu@e67b0000 {
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- compatible = "renesas,ipmmu-r8a77970";
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- reg = <0 0xe67b0000 0 0x1000>;
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- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
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- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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- #iommu-cells = <1>;
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- };
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-
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- pfc: pin-controller@e6060000 {
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- compatible = "renesas,pfc-r8a77970";
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- reg = <0 0xe6060000 0 0x504>;
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- };
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-
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gpio0: gpio@e6050000 {
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compatible = "renesas,gpio-r8a77970",
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"renesas,rcar-gen3-gpio";
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@@ -266,6 +204,32 @@
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resets = <&cpg 907>;
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};
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+ pfc: pin-controller@e6060000 {
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+ compatible = "renesas,pfc-r8a77970";
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+ reg = <0 0xe6060000 0 0x504>;
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+ };
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+
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+ cpg: clock-controller@e6150000 {
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+ compatible = "renesas,r8a77970-cpg-mssr";
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+ reg = <0 0xe6150000 0 0x1000>;
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+ clocks = <&extal_clk>, <&extalr_clk>;
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+ clock-names = "extal", "extalr";
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+ #clock-cells = <2>;
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+ #power-domain-cells = <0>;
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+ #reset-cells = <1>;
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+ };
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+
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+ rst: reset-controller@e6160000 {
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+ compatible = "renesas,r8a77970-rst";
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+ reg = <0 0xe6160000 0 0x200>;
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+ };
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+
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+ sysc: system-controller@e6180000 {
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+ compatible = "renesas,r8a77970-sysc";
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+ reg = <0 0xe6180000 0 0x440>;
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+ #power-domain-cells = <1>;
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+ };
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+
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intc_ex: interrupt-controller@e61c0000 {
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compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
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#interrupt-cells = <2>;
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@@ -282,67 +246,6 @@
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resets = <&cpg 407>;
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};
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- prr: chipid@fff00044 {
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- compatible = "renesas,prr";
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- reg = <0 0xfff00044 0 4>;
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- };
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-
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- dmac1: dma-controller@e7300000 {
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- compatible = "renesas,dmac-r8a77970",
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- "renesas,rcar-dmac";
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- reg = <0 0xe7300000 0 0x10000>;
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- interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
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- GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
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- GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
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- GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
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- GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
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- GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
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- GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
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- GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
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- GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
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- interrupt-names = "error",
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- "ch0", "ch1", "ch2", "ch3",
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- "ch4", "ch5", "ch6", "ch7";
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- clocks = <&cpg CPG_MOD 218>;
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- clock-names = "fck";
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- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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- resets = <&cpg 218>;
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- #dma-cells = <1>;
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- dma-channels = <8>;
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- iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
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- <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
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- <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
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- <&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
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- };
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-
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- dmac2: dma-controller@e7310000 {
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- compatible = "renesas,dmac-r8a77970",
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- "renesas,rcar-dmac";
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- reg = <0 0xe7310000 0 0x10000>;
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- interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
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- GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
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- GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
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- GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
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- GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
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- GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
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- GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
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- GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
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- GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
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- interrupt-names = "error",
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- "ch0", "ch1", "ch2", "ch3",
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- "ch4", "ch5", "ch6", "ch7";
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- clocks = <&cpg CPG_MOD 217>;
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- clock-names = "fck";
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- power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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- resets = <&cpg 217>;
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- #dma-cells = <1>;
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- dma-channels = <8>;
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- iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
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- <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
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- <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
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- <&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
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- };
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-
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i2c0: i2c@e6500000 {
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compatible = "renesas,i2c-r8a77970",
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"renesas,rcar-gen3-i2c";
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@@ -499,6 +402,77 @@
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status = "disabled";
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};
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+ canfd: can@e66c0000 {
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+ compatible = "renesas,r8a77970-canfd",
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+ "renesas,rcar-gen3-canfd";
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+ reg = <0 0xe66c0000 0 0x8000>;
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+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cpg CPG_MOD 914>,
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+ <&cpg CPG_CORE R8A77970_CLK_CANFD>,
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+ <&can_clk>;
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+ clock-names = "fck", "canfd", "can_clk";
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+ assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>;
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+ assigned-clock-rates = <40000000>;
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+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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+ resets = <&cpg 914>;
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+ status = "disabled";
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+
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+ channel0 {
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+ status = "disabled";
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+ };
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+
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+ channel1 {
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+ status = "disabled";
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+ };
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+ };
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+
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+ avb: ethernet@e6800000 {
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+ compatible = "renesas,etheravb-r8a77970",
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+ "renesas,etheravb-rcar-gen3";
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+ reg = <0 0xe6800000 0 0x800>;
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+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "ch0", "ch1", "ch2", "ch3",
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+ "ch4", "ch5", "ch6", "ch7",
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+ "ch8", "ch9", "ch10", "ch11",
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+ "ch12", "ch13", "ch14", "ch15",
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+ "ch16", "ch17", "ch18", "ch19",
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+ "ch20", "ch21", "ch22", "ch23",
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+ "ch24";
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+ clocks = <&cpg CPG_MOD 812>;
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+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
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+ resets = <&cpg 812>;
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+ phy-mode = "rgmii";
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+ iommus = <&ipmmu_rt 3>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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scif0: serial@e6e60000 {
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compatible = "renesas,scif-r8a77970",
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"renesas,rcar-gen3-scif",
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@@ -570,57 +544,358 @@
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status = "disabled";
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};
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- avb: ethernet@e6800000 {
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- compatible = "renesas,etheravb-r8a77970",
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- "renesas,etheravb-rcar-gen3";
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- reg = <0 0xe6800000 0 0x800>;
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- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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- interrupt-names = "ch0", "ch1", "ch2", "ch3",
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- "ch4", "ch5", "ch6", "ch7",
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|
|
- "ch8", "ch9", "ch10", "ch11",
|
|
|
- "ch12", "ch13", "ch14", "ch15",
|
|
|
- "ch16", "ch17", "ch18", "ch19",
|
|
|
- "ch20", "ch21", "ch22", "ch23",
|
|
|
- "ch24";
|
|
|
- clocks = <&cpg CPG_MOD 812>;
|
|
|
+
|
|
|
+ vin0: video@e6ef0000 {
|
|
|
+ compatible = "renesas,vin-r8a77970";
|
|
|
+ reg = <0 0xe6ef0000 0 0x1000>;
|
|
|
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&cpg CPG_MOD 811>;
|
|
|
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
|
- resets = <&cpg 812>;
|
|
|
- phy-mode = "rgmii";
|
|
|
- iommus = <&ipmmu_rt 3>;
|
|
|
- #address-cells = <1>;
|
|
|
- #size-cells = <0>;
|
|
|
+ resets = <&cpg 811>;
|
|
|
+ renesas,id = <0>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ ports {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+
|
|
|
+ port@1 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+
|
|
|
+ reg = <1>;
|
|
|
+
|
|
|
+ vin0csi40: endpoint@2 {
|
|
|
+ reg = <2>;
|
|
|
+ remote-endpoint= <&csi40vin0>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ vin1: video@e6ef1000 {
|
|
|
+ compatible = "renesas,vin-r8a77970";
|
|
|
+ reg = <0 0xe6ef1000 0 0x1000>;
|
|
|
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&cpg CPG_MOD 810>;
|
|
|
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
|
+ resets = <&cpg 810>;
|
|
|
+ renesas,id = <1>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ ports {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+
|
|
|
+ port@1 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+
|
|
|
+ reg = <1>;
|
|
|
+
|
|
|
+ vin1csi40: endpoint@2 {
|
|
|
+ reg = <2>;
|
|
|
+ remote-endpoint= <&csi40vin1>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ vin2: video@e6ef2000 {
|
|
|
+ compatible = "renesas,vin-r8a77970";
|
|
|
+ reg = <0 0xe6ef2000 0 0x1000>;
|
|
|
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&cpg CPG_MOD 809>;
|
|
|
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
|
+ resets = <&cpg 809>;
|
|
|
+ renesas,id = <2>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ ports {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+
|
|
|
+ port@1 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+
|
|
|
+ reg = <1>;
|
|
|
+
|
|
|
+ vin2csi40: endpoint@2 {
|
|
|
+ reg = <2>;
|
|
|
+ remote-endpoint= <&csi40vin2>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ vin3: video@e6ef3000 {
|
|
|
+ compatible = "renesas,vin-r8a77970";
|
|
|
+ reg = <0 0xe6ef3000 0 0x1000>;
|
|
|
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&cpg CPG_MOD 808>;
|
|
|
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
|
+ resets = <&cpg 808>;
|
|
|
+ renesas,id = <3>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ ports {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+
|
|
|
+ port@1 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+
|
|
|
+ reg = <1>;
|
|
|
+
|
|
|
+ vin3csi40: endpoint@2 {
|
|
|
+ reg = <2>;
|
|
|
+ remote-endpoint= <&csi40vin3>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ dmac1: dma-controller@e7300000 {
|
|
|
+ compatible = "renesas,dmac-r8a77970",
|
|
|
+ "renesas,rcar-dmac";
|
|
|
+ reg = <0 0xe7300000 0 0x10000>;
|
|
|
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
|
|
|
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
|
|
|
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
|
|
|
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
|
|
|
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
|
|
|
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
|
|
|
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
|
|
|
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
|
|
|
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ interrupt-names = "error",
|
|
|
+ "ch0", "ch1", "ch2", "ch3",
|
|
|
+ "ch4", "ch5", "ch6", "ch7";
|
|
|
+ clocks = <&cpg CPG_MOD 218>;
|
|
|
+ clock-names = "fck";
|
|
|
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
|
+ resets = <&cpg 218>;
|
|
|
+ #dma-cells = <1>;
|
|
|
+ dma-channels = <8>;
|
|
|
+ iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
|
|
|
+ <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
|
|
|
+ <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
|
|
|
+ <&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
|
|
|
+ };
|
|
|
+
|
|
|
+ dmac2: dma-controller@e7310000 {
|
|
|
+ compatible = "renesas,dmac-r8a77970",
|
|
|
+ "renesas,rcar-dmac";
|
|
|
+ reg = <0 0xe7310000 0 0x10000>;
|
|
|
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
|
|
|
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
|
|
|
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
|
|
|
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
|
|
|
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
|
|
|
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
|
|
|
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
|
|
|
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
|
|
|
+ GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ interrupt-names = "error",
|
|
|
+ "ch0", "ch1", "ch2", "ch3",
|
|
|
+ "ch4", "ch5", "ch6", "ch7";
|
|
|
+ clocks = <&cpg CPG_MOD 217>;
|
|
|
+ clock-names = "fck";
|
|
|
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
|
+ resets = <&cpg 217>;
|
|
|
+ #dma-cells = <1>;
|
|
|
+ dma-channels = <8>;
|
|
|
+ iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
|
|
|
+ <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
|
|
|
+ <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
|
|
|
+ <&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
|
|
|
+ };
|
|
|
+
|
|
|
+ ipmmu_ds1: mmu@e7740000 {
|
|
|
+ compatible = "renesas,ipmmu-r8a77970";
|
|
|
+ reg = <0 0xe7740000 0 0x1000>;
|
|
|
+ renesas,ipmmu-main = <&ipmmu_mm 0>;
|
|
|
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
|
+ #iommu-cells = <1>;
|
|
|
+ };
|
|
|
+
|
|
|
+ ipmmu_ir: mmu@ff8b0000 {
|
|
|
+ compatible = "renesas,ipmmu-r8a77970";
|
|
|
+ reg = <0 0xff8b0000 0 0x1000>;
|
|
|
+ renesas,ipmmu-main = <&ipmmu_mm 3>;
|
|
|
+ power-domains = <&sysc R8A77970_PD_A3IR>;
|
|
|
+ #iommu-cells = <1>;
|
|
|
+ };
|
|
|
+
|
|
|
+ ipmmu_mm: mmu@e67b0000 {
|
|
|
+ compatible = "renesas,ipmmu-r8a77970";
|
|
|
+ reg = <0 0xe67b0000 0 0x1000>;
|
|
|
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
|
+ #iommu-cells = <1>;
|
|
|
+ };
|
|
|
+
|
|
|
+ ipmmu_rt: mmu@ffc80000 {
|
|
|
+ compatible = "renesas,ipmmu-r8a77970";
|
|
|
+ reg = <0 0xffc80000 0 0x1000>;
|
|
|
+ renesas,ipmmu-main = <&ipmmu_mm 7>;
|
|
|
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
|
+ #iommu-cells = <1>;
|
|
|
+ };
|
|
|
+
|
|
|
+ ipmmu_vi0: mmu@febd0000 {
|
|
|
+ compatible = "renesas,ipmmu-r8a77970";
|
|
|
+ reg = <0 0xfebd0000 0 0x1000>;
|
|
|
+ renesas,ipmmu-main = <&ipmmu_mm 9>;
|
|
|
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
|
+ #iommu-cells = <1>;
|
|
|
+ };
|
|
|
+
|
|
|
+ gic: interrupt-controller@f1010000 {
|
|
|
+ compatible = "arm,gic-400";
|
|
|
+ #interrupt-cells = <3>;
|
|
|
+ #address-cells = <0>;
|
|
|
+ interrupt-controller;
|
|
|
+ reg = <0 0xf1010000 0 0x1000>,
|
|
|
+ <0 0xf1020000 0 0x20000>,
|
|
|
+ <0 0xf1040000 0 0x20000>,
|
|
|
+ <0 0xf1060000 0 0x20000>;
|
|
|
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
|
|
|
+ IRQ_TYPE_LEVEL_HIGH)>;
|
|
|
+ clocks = <&cpg CPG_MOD 408>;
|
|
|
+ clock-names = "clk";
|
|
|
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
|
+ resets = <&cpg 408>;
|
|
|
+ };
|
|
|
+
|
|
|
+ vspd0: vsp@fea20000 {
|
|
|
+ compatible = "renesas,vsp2";
|
|
|
+ reg = <0 0xfea20000 0 0x5000>;
|
|
|
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&cpg CPG_MOD 623>;
|
|
|
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
|
+ resets = <&cpg 623>;
|
|
|
+ renesas,fcp = <&fcpvd0>;
|
|
|
+ };
|
|
|
+
|
|
|
+ fcpvd0: fcp@fea27000 {
|
|
|
+ compatible = "renesas,fcpv";
|
|
|
+ reg = <0 0xfea27000 0 0x200>;
|
|
|
+ clocks = <&cpg CPG_MOD 603>;
|
|
|
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
|
+ resets = <&cpg 603>;
|
|
|
+ };
|
|
|
+
|
|
|
+ csi40: csi2@feaa0000 {
|
|
|
+ compatible = "renesas,r8a77970-csi2";
|
|
|
+ reg = <0 0xfeaa0000 0 0x10000>;
|
|
|
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&cpg CPG_MOD 716>;
|
|
|
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
|
+ resets = <&cpg 716>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ ports {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+
|
|
|
+ port@1 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+
|
|
|
+ reg = <1>;
|
|
|
+
|
|
|
+ csi40vin0: endpoint@0 {
|
|
|
+ reg = <0>;
|
|
|
+ remote-endpoint = <&vin0csi40>;
|
|
|
+ };
|
|
|
+ csi40vin1: endpoint@1 {
|
|
|
+ reg = <1>;
|
|
|
+ remote-endpoint = <&vin1csi40>;
|
|
|
+ };
|
|
|
+ csi40vin2: endpoint@2 {
|
|
|
+ reg = <2>;
|
|
|
+ remote-endpoint = <&vin2csi40>;
|
|
|
+ };
|
|
|
+ csi40vin3: endpoint@3 {
|
|
|
+ reg = <3>;
|
|
|
+ remote-endpoint = <&vin3csi40>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ du: display@feb00000 {
|
|
|
+ compatible = "renesas,du-r8a77970";
|
|
|
+ reg = <0 0xfeb00000 0 0x80000>;
|
|
|
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&cpg CPG_MOD 724>;
|
|
|
+ clock-names = "du.0";
|
|
|
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
|
+ resets = <&cpg 724>;
|
|
|
+ vsps = <&vspd0>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ ports {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+
|
|
|
+ port@0 {
|
|
|
+ reg = <0>;
|
|
|
+ du_out_rgb: endpoint {
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ port@1 {
|
|
|
+ reg = <1>;
|
|
|
+ du_out_lvds0: endpoint {
|
|
|
+ remote-endpoint = <&lvds0_in>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ lvds0: lvds-encoder@feb90000 {
|
|
|
+ compatible = "renesas,r8a77970-lvds";
|
|
|
+ reg = <0 0xfeb90000 0 0x14>;
|
|
|
+ clocks = <&cpg CPG_MOD 727>;
|
|
|
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
|
|
+ resets = <&cpg 727>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ ports {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+
|
|
|
+ port@0 {
|
|
|
+ reg = <0>;
|
|
|
+ lvds0_in: endpoint {
|
|
|
+ remote-endpoint =
|
|
|
+ <&du_out_lvds0>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ port@1 {
|
|
|
+ reg = <1>;
|
|
|
+ lvds0_out: endpoint {
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ prr: chipid@fff00044 {
|
|
|
+ compatible = "renesas,prr";
|
|
|
+ reg = <0 0xfff00044 0 4>;
|
|
|
};
|
|
|
};
|
|
|
|
|
|
timer {
|
|
|
compatible = "arm,armv8-timer";
|
|
|
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
|
|
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
|
|
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
|
|
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
|
|
|
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
|
|
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
|
|
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
|
|
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
|
|
};
|
|
|
};
|