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@@ -9,6 +9,163 @@
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#include "fsl_epu.h"
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+struct fsm_reg_vals epu_default_val[] = {
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+ /* EPGCR (Event Processor Global Control Register) */
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+ {EPGCR, 0},
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+ /* EPECR (Event Processor Event Control Registers) */
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+ {EPECR0 + EPECR_STRIDE * 0, 0},
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+ {EPECR0 + EPECR_STRIDE * 1, 0},
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+ {EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
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+ {EPECR0 + EPECR_STRIDE * 3, 0x80000084},
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+ {EPECR0 + EPECR_STRIDE * 4, 0x20000084},
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+ {EPECR0 + EPECR_STRIDE * 5, 0x08000004},
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+ {EPECR0 + EPECR_STRIDE * 6, 0x80000084},
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+ {EPECR0 + EPECR_STRIDE * 7, 0x80000084},
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+ {EPECR0 + EPECR_STRIDE * 8, 0x60000084},
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+ {EPECR0 + EPECR_STRIDE * 9, 0x08000084},
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+ {EPECR0 + EPECR_STRIDE * 10, 0x42000084},
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+ {EPECR0 + EPECR_STRIDE * 11, 0x90000084},
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+ {EPECR0 + EPECR_STRIDE * 12, 0x80000084},
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+ {EPECR0 + EPECR_STRIDE * 13, 0x08000084},
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+ {EPECR0 + EPECR_STRIDE * 14, 0x02000084},
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+ {EPECR0 + EPECR_STRIDE * 15, 0x00000004},
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+ /*
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+ * EPEVTCR (Event Processor EVT Pin Control Registers)
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+ * SCU8 triger EVT2, and SCU11 triger EVT9
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+ */
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+ {EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
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+ {EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
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+ {EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x80000001},
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+ {EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
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+ {EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
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+ {EPEVTCR0 + EPEVTCR_STRIDE * 5, 0},
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+ {EPEVTCR0 + EPEVTCR_STRIDE * 6, 0},
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+ {EPEVTCR0 + EPEVTCR_STRIDE * 7, 0},
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+ {EPEVTCR0 + EPEVTCR_STRIDE * 8, 0},
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+ {EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB0000001},
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+ /* EPCMPR (Event Processor Counter Compare Registers) */
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+ {EPCMPR0 + EPCMPR_STRIDE * 0, 0},
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+ {EPCMPR0 + EPCMPR_STRIDE * 1, 0},
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+ {EPCMPR0 + EPCMPR_STRIDE * 2, 0x000000FF},
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+ {EPCMPR0 + EPCMPR_STRIDE * 3, 0},
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+ {EPCMPR0 + EPCMPR_STRIDE * 4, 0x000000FF},
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+ {EPCMPR0 + EPCMPR_STRIDE * 5, 0x00000020},
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+ {EPCMPR0 + EPCMPR_STRIDE * 6, 0},
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+ {EPCMPR0 + EPCMPR_STRIDE * 7, 0},
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+ {EPCMPR0 + EPCMPR_STRIDE * 8, 0x000000FF},
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+ {EPCMPR0 + EPCMPR_STRIDE * 9, 0x000000FF},
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+ {EPCMPR0 + EPCMPR_STRIDE * 10, 0x000000FF},
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+ {EPCMPR0 + EPCMPR_STRIDE * 11, 0x000000FF},
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+ {EPCMPR0 + EPCMPR_STRIDE * 12, 0x000000FF},
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+ {EPCMPR0 + EPCMPR_STRIDE * 13, 0},
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+ {EPCMPR0 + EPCMPR_STRIDE * 14, 0x000000FF},
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+ {EPCMPR0 + EPCMPR_STRIDE * 15, 0x000000FF},
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+ /* EPCCR (Event Processor Counter Control Registers) */
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+ {EPCCR0 + EPCCR_STRIDE * 0, 0},
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+ {EPCCR0 + EPCCR_STRIDE * 1, 0},
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+ {EPCCR0 + EPCCR_STRIDE * 2, 0x92840000},
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+ {EPCCR0 + EPCCR_STRIDE * 3, 0},
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+ {EPCCR0 + EPCCR_STRIDE * 4, 0x92840000},
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+ {EPCCR0 + EPCCR_STRIDE * 5, 0x92840000},
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+ {EPCCR0 + EPCCR_STRIDE * 6, 0},
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+ {EPCCR0 + EPCCR_STRIDE * 7, 0},
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+ {EPCCR0 + EPCCR_STRIDE * 8, 0x92840000},
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+ {EPCCR0 + EPCCR_STRIDE * 9, 0x92840000},
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+ {EPCCR0 + EPCCR_STRIDE * 10, 0x92840000},
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+ {EPCCR0 + EPCCR_STRIDE * 11, 0x92840000},
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+ {EPCCR0 + EPCCR_STRIDE * 12, 0x92840000},
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+ {EPCCR0 + EPCCR_STRIDE * 13, 0},
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+ {EPCCR0 + EPCCR_STRIDE * 14, 0x92840000},
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+ {EPCCR0 + EPCCR_STRIDE * 15, 0x92840000},
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+ /* EPSMCR (Event Processor SCU Mux Control Registers) */
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+ {EPSMCR0 + EPSMCR_STRIDE * 0, 0},
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+ {EPSMCR0 + EPSMCR_STRIDE * 1, 0},
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+ {EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C700000},
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+ {EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F000000},
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+ {EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F0000},
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+ {EPSMCR0 + EPSMCR_STRIDE * 5, 0x00002E00},
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+ {EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C000000},
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+ {EPSMCR0 + EPSMCR_STRIDE * 7, 0x30000000},
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+ {EPSMCR0 + EPSMCR_STRIDE * 8, 0x64300000},
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+ {EPSMCR0 + EPSMCR_STRIDE * 9, 0x00003000},
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+ {EPSMCR0 + EPSMCR_STRIDE * 10, 0x65000030},
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+ {EPSMCR0 + EPSMCR_STRIDE * 11, 0x31740000},
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+ {EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F000000},
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+ {EPSMCR0 + EPSMCR_STRIDE * 13, 0x00003100},
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+ {EPSMCR0 + EPSMCR_STRIDE * 14, 0x00000031},
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+ {EPSMCR0 + EPSMCR_STRIDE * 15, 0x76000000},
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+ /* EPACR (Event Processor Action Control Registers) */
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+ {EPACR0 + EPACR_STRIDE * 0, 0},
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+ {EPACR0 + EPACR_STRIDE * 1, 0},
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+ {EPACR0 + EPACR_STRIDE * 2, 0},
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+ {EPACR0 + EPACR_STRIDE * 3, 0x00000080},
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+ {EPACR0 + EPACR_STRIDE * 4, 0},
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+ {EPACR0 + EPACR_STRIDE * 5, 0x00000040},
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+ {EPACR0 + EPACR_STRIDE * 6, 0},
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+ {EPACR0 + EPACR_STRIDE * 7, 0},
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+ {EPACR0 + EPACR_STRIDE * 8, 0},
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+ {EPACR0 + EPACR_STRIDE * 9, 0x0000001C},
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+ {EPACR0 + EPACR_STRIDE * 10, 0x00000020},
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+ {EPACR0 + EPACR_STRIDE * 11, 0},
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+ {EPACR0 + EPACR_STRIDE * 12, 0x00000003},
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+ {EPACR0 + EPACR_STRIDE * 13, 0x06000000},
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+ {EPACR0 + EPACR_STRIDE * 14, 0x04000000},
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+ {EPACR0 + EPACR_STRIDE * 15, 0x02000000},
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+ /* EPIMCR (Event Processor Input Mux Control Registers) */
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+ {EPIMCR0 + EPIMCR_STRIDE * 0, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 1, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 2, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 3, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 4, 0x44000000},
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+ {EPIMCR0 + EPIMCR_STRIDE * 5, 0x40000000},
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+ {EPIMCR0 + EPIMCR_STRIDE * 6, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 7, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 8, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 9, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 10, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 11, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 12, 0x44000000},
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+ {EPIMCR0 + EPIMCR_STRIDE * 13, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 14, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 15, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 16, 0x6A000000},
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+ {EPIMCR0 + EPIMCR_STRIDE * 17, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 18, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 19, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 20, 0x48000000},
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+ {EPIMCR0 + EPIMCR_STRIDE * 21, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 22, 0x6C000000},
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+ {EPIMCR0 + EPIMCR_STRIDE * 23, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 24, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 25, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 26, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 27, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 28, 0x76000000},
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+ {EPIMCR0 + EPIMCR_STRIDE * 29, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 30, 0},
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+ {EPIMCR0 + EPIMCR_STRIDE * 31, 0x76000000},
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+ /* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
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+ {EPXTRIGCR, 0x0000FFDF},
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+ /* end */
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+ {FSM_END_FLAG, 0},
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+};
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+
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+/**
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+ * fsl_epu_setup - Setup EPU registers to default values
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+ */
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+void fsl_epu_setup(void *epu_base)
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+{
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+ struct fsm_reg_vals *data = epu_default_val;
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+
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+ if (!epu_base || !data)
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+ return;
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+
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+ while (data->offset != FSM_END_FLAG) {
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+ out_be32(epu_base + data->offset, data->value);
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+ data++;
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+ }
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+}
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+
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/**
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* fsl_epu_clean - Clear EPU registers
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*/
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