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@@ -0,0 +1,301 @@
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+/* SPDX-License-Identifier: GPL-2.0+ */
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+/*
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+ * Intel Broadwell I2S driver
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+ *
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+ * Copyright 2019 Google LLC
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+ *
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+ * Modified from dc i2s/broadwell/broadwell.h
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+ */
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+
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+#ifndef __BROADWELL_I2S_H__
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+#define __BROADWELL_I2S_H__
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+
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+enum {
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+ SSP_FIFO_SIZE = 7,
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+};
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+
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+enum frame_sync_rel_timing_t {
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+ NEXT_FRMS_AFTER_END_OF_T4 = 0,
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+ NEXT_FRMS_WITH_LSB_PREVIOUS_FRM,
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+};
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+
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+enum frame_sync_pol_t {
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+ SSP_FRMS_ACTIVE_LOW = 0,
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+ SSP_FRMS_ACTIVE_HIGH,
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+};
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+
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+enum end_transfer_state_t {
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+ SSP_END_TRANSFER_STATE_LOW = 0,
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+ SSP_END_TRANSFER_STATE_PEVIOUS_BIT,
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+};
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+
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+enum clock_mode_t {
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+ /* Data driven (falling), data sampled (rising), idle state (low) */
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+ SCLK_MODE_DDF_DSR_ISL,
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+ /* Data driven (rising), data sampled (falling), idle state (low) */
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+ SCLK_MODE_DDR_DSF_ISL,
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+ /* Data driven (rising), data sampled (falling), idle state (high) */
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+ SCLK_MODE_DDR_DSF_ISH,
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+ /* Data driven (falling), data sampled (rising), idle state (high) */
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+ SCLK_MODE_DDF_DSR_ISH,
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+};
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+
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+struct i2s_shim_regs {
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+ u32 csr; /* 0x00 */
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+ u32 reserved0[29]; /* 0x14 - 0x77 */
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+ u32 clkctl; /* 0x78 */
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+ u32 reserved1; /* 0x7c */
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+ u32 cs2; /* 0x80 */
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+};
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+
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+struct broadwell_i2s_regs {
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+ u32 sscr0; /* 0x00 */
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+ u32 sscr1; /* 0x04 */
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+ u32 sssr; /* 0x08 */
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+ u32 ssitr; /* 0x0c */
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+ u32 ssdr; /* 0x10 */
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+ u32 reserved0[5]; /* 0x14 - 0x27 */
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+ u32 ssto; /* 0x28 */
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+ u32 sspsp; /* 0x2c */
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+ u32 sstsa; /* 0x30 */
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+ u32 ssrsa; /* 0x34 */
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+ u32 sstss; /* 0x38 */
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+ u32 sscr2; /* 0x40 */
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+ u32 sspsp2; /* 0x44 */
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+};
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+
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+/* SHIM Configuration & Status */
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+enum {
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+ /* Low Power Clock Select */
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+ SHIM_CS_LPCS = 1 << 31,
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+ /* SSP Force Clock Running */
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+ SHIM_CS_SFCR_SSP1 = 1 << 28,
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+ SHIM_CS_SFCR_SSP0 = 1 << 27,
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+ /* SSP1 IO Clock Select */
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+ SHIM_CS_S1IOCS = 1 << 23,
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+ /* SSP0 IO Clock Select */
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+ SHIM_CS_S0IOCS = 1 << 21,
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+ /* Parity Check Enable */
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+ SHIM_CS_PCE = 1 << 15,
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+ /* SSP DMA or PIO Mode */
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+ SHIM_CS_SDPM_PIO_SSP1 = 1 << 12,
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+ SHIM_CS_SDPM_DMA_SSP1 = 0 << 12,
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+ SHIM_CS_SDPM_PIO_SSP0 = 1 << 11,
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+ SHIM_CS_SDPM_DMA_SSP0 = 0 << 11,
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+ /* Run / Stall */
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+ SHIM_CS_STALL = 1 << 10,
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+ /* DSP Clock Select */
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+ SHIM_CS_DCS_DSP320_AF80 = 0 << 4,
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+ SHIM_CS_DCS_DSP160_AF80 = 1 << 4,
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+ SHIM_CS_DCS_DSP80_AF80 = 2 << 4,
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+ SHIM_CS_DCS_DSP320_AF160 = 4 << 4,
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+ SHIM_CS_DCS_DSP160_AF160 = 5 << 4,
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+ SHIM_CS_DCS_DSP32_AF32 = 6 << 4,
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+ SHIM_CS_DCS_MASK = 7 << 4,
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+ /* SSP Base Clock Select */
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+ SHIM_CS_SBCS_SSP0_24MHZ = 1 << 3,
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+ SHIM_CS_SBCS_SSP0_32MHZ = 0 << 3,
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+ SHIM_CS_SBCS_SSP1_24MHZ = 1 << 2,
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+ SHIM_CS_SBCS_SSP1_32MHZ = 0 << 2,
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+ /* DSP Core Reset */
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+ SHIM_CS_RST = 1 << 1,
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+};
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+
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+/* SHIM Clock Control */
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+enum {
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+ /* Clock Frequency Change In Progress */
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+ SHIM_CLKCTL_CFCIP = 1 << 31,
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+ /* SSP MCLK Output Select */
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+ SHIM_CLKCTL_MCLK_MASK = 0x3,
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+ SHIM_CLKCTL_MCLK_SHIFT = 24,
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+ SHIM_CLKCTL_MCLK_DISABLED = 0 << 24,
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+ SHIM_CLKCTL_MCLK_6MHZ = 1 << 24,
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+ SHIM_CLKCTL_MCLK_12MHZ = 2 << 24,
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+ SHIM_CLKCTL_MCLK_24MHZ = 3 << 24,
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+ /* DSP Core Prevent Local Clock Gating */
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+ SHIM_CLKCTL_DCPLCG = 1 << 18,
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+ /* SSP Clock Output Enable */
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+ SHIM_CLKCTL_SCOE_SSP1 = 1 << 17,
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+ SHIM_CLKCTL_SCOE_SSP0 = 1 << 16,
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+ /* DMA Engine Force Local Clock Gating */
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+ SHIM_CLKCTL_DEFLCGB_DMA1_CGE = 0 << 6,
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+ SHIM_CLKCTL_DEFLCGB_DMA1_CGD = 1 << 6,
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+ SHIM_CLKCTL_DEFLCGB_DMA0_CGE = 0 << 5,
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+ SHIM_CLKCTL_DEFLCGB_DMA0_CGD = 1 << 5,
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+ /* SSP Force Local Clock Gating */
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+ SHIM_CLKCTL_SFLCGB_SSP1_CGE = 0 << 1,
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+ SHIM_CLKCTL_SFLCGB_SSP1_CGD = 1 << 1,
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+ SHIM_CLKCTL_SFLCGB_SSP0_CGE = 0 << 0,
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+ SHIM_CLKCTL_SFLCGB_SSP0_CGD = 1 << 0,
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+
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+ /* Reserved bits: 30:26, 23:19, 15:7, 4:2 */
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+ SHIM_CLKCTL_RESERVED = 0x1f << 26 | 0x1f << 19 | 0x1ff << 7 | 0x7 << 2,
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+};
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+
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+/* SSP Status */
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+enum {
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+ /* Bit Count Error */
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+ SSP_SSS_BCE = 1 << 23,
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+ /* Clock Sync Statu s*/
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+ SSP_SSS_CSS = 1 << 22,
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+ /* Transmit FIFO Underrun */
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+ SSP_SSS_TUR = 1 << 21,
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+ /* End Of Chain */
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+ SSP_SSS_EOC = 1 << 20,
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+ /* Receiver Time-out Interrupt */
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+ SSP_SSS_TINT = 1 << 19,
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+ /* Peripheral Trailing Byte Interrupt */
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+ SSP_SSS_PINT = 1 << 18,
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+ /* Received FIFO Level */
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+ SSP_RFL_MASK = 0xf,
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+ SSP_RFL_SHIFT = 12,
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+ /* Transmit FIFO Level */
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+ SSP_TFL_MASK = 0xf,
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+ SSP_TFL_SHIFT = 8,
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+ /* Receive FIFO Overrun */
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+ SSP_SSS_ROR = 1 << 7,
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+ /* Receive FIFO Service Request */
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+ SSP_SSS_RFS = 1 << 6,
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+ /* Transmit FIFO Service Request */
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+ SSP_SSS_TFS = 1 << 5,
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+ /* SSP Busy */
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+ SSP_SSS_BSY = 1 << 4,
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+ /* Receive FIFO Not Empty */
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+ SSP_SSS_RNE = 1 << 3,
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+ /* Transmit FIFO Not Full */
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+ SSP_SSS_TNF = 1 << 2,
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+};
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+
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+/* SSP Control 0 */
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+enum {
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+ /* Mode */
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+ SSP_SSC0_MODE_NORMAL = 0 << 31,
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+ SSP_SSC0_MODE_NETWORK = 1 << 31,
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+ /* Audio Clock Select */
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+ SSP_SSC0_ACS_PCH = 0 << 30,
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+ /* Frame Rate Divider Control (0-7) */
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+ SSP_SSC0_FRDC_MASK = 0x7,
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+ SSP_SSC0_FRDC_SHIFT = 24,
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+ SSP_SSC0_FRDC_STEREO = 1 << 24,
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+ /* Transmit FIFO Underrun Interrupt Mask */
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+ SSP_SSC0_TIM = 1 << 23,
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+ /* Receive FIFO Underrun Interrupt Mask */
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+ SSP_SSC0_RIM = 1 << 22,
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+ /* Network Clock Select */
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+ SSP_SSC0_NCS_PCH = 0 << 21,
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+ /* Extended Data Size Select */
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+ SSP_SSC0_EDSS = 1 << 20,
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+ /* Serial Clock Rate (0-4095) */
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+ SSP_SSC0_SCR_SHIFT = 8,
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+ SSP_SSC0_SCR_MASK = 0xfff << SSP_SSC0_SCR_SHIFT,
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+ /* Synchronous Serial Port Enable */
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+ SSP_SSC0_SSE = 1 << 7,
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+ /* External Clock Select */
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+ SSP_SSC0_ECS_PCH = 0 << 6,
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+ /* Frame Format */
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+ SSP_SSC0_FRF_MOTOROLA_SPI = 0 << 4,
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+ SSP_SSC0_FRF_TI_SSP = 1 << 4,
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+ SSP_SSC0_FRF_NS_MICROWIRE = 2 << 4,
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+ SSP_SSC0_FRF_PSP = 3 << 4,
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+ /* Data Size Select */
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+ SSP_SSC0_DSS_SHIFT = 0,
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+ SSP_SSC0_DSS_MASK = 0xf << SSP_SSC0_DSS_SHIFT,
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+};
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+
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+/* SSP Control 1 */
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+enum {
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+ /* TXD Tristate Enable on Last Phase */
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+ SSP_SSC1_TTELP = 1 << 31,
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+ /* TXD Tristate Enable */
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+ SSP_SSC1_TTE = 1 << 30,
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+ /* Enable Bit Count Error Interrupt */
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+ SSP_SSC1_EBCEI = 1 << 29,
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+ /* Slave Clock Running */
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+ SSP_SSC1_SCFR = 1 << 28,
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+ /* Enable Clock Request A */
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+ SSP_SSC1_ECRA = 1 << 27,
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+ /* Enable Clock Request B */
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+ SSP_SSC1_ECRB = 1 << 26,
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+ /* SSPCLK Direction */
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+ SSP_SSC1_SCLKDIR_SLAVE = 1 << 25,
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+ SSP_SSC1_SCLKDIR_MASTER = 0 << 25,
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+ /* SSPFRM Direction */
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+ SSP_SSC1_SFRMDIR_SLAVE = 1 << 24,
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+ SSP_SSC1_SFRMDIR_MASTER = 0 << 24,
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+ /* Receive without Transmit */
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+ SSP_SSC1_RWOT = 1 << 23,
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+ /* Trailing Byte */
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+ SSP_SSC1_TRAIL = 1 << 22,
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+ /* DMA Tx Service Request Enable */
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+ SSP_SSC1_TSRE = 1 << 21,
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+ /* DMA Rx Service Request Enable */
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+ SSP_SSC1_RSRE = 1 << 20,
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+ /* Receiver Timeout Interrupt Enable */
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+ SSP_SSC1_TINTE = 1 << 19,
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+ /* Periph. Trailing Byte Int. Enable */
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+ SSP_SSC1_PINTE = 1 << 18,
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+ /* Invert Frame Signal */
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+ SSP_SSC1_IFS = 1 << 16,
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+ /* Select FIFO for EFWR: test mode */
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+ SSP_SSC1_STRF = 1 << 15,
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+ /* Enable FIFO Write/Read: test mode */
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+ SSP_SSC1_EFWR = 1 << 14,
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+ /* Receive FIFO Trigger Threshold */
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+ SSP_SSC1_RFT_SHIFT = 10,
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+ SSP_SSC1_RFT_MASK = 0xf << SSP_SSC1_RFT_SHIFT,
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+ /* Transmit FIFO Trigger Threshold */
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+ SSP_SSC1_TFT_SHIFT = 6,
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+ SSP_SSC1_TFT_MASK = 0xf << SSP_SSC1_TFT_SHIFT,
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+ /* Microwire Transmit Data Size */
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+ SSP_SSC1_MWDS = 1 << 5,
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+ /* Motorola SPI SSPSCLK Phase Setting*/
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+ SSP_SSC1_SPH = 1 << 4,
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+ /* Motorola SPI SSPSCLK Polarity */
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+ SSP_SSC1_SPO = 1 << 3,
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+ /* Loopback mode: test mode */
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+ SSP_SSC1_LBM = 1 << 2,
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+ /* Transmit FIFO Interrupt Enable */
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+ SSP_SSC1_TIE = 1 << 1,
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+ /* Receive FIFO Interrupt Enable */
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+ SSP_SSC1_RIE = 1 << 0,
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+
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+ SSP_SSC1_RESERVED = 17 << 1,
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+};
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+
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+/* SSP Programmable Serial Protocol */
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+enum {
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+ /* Extended Dummy Stop (0-31) */
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+ SSP_PSP_EDYMSTOP_SHIFT = 26,
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+ SSP_PSP_EDMYSTOP_MASK = 0x7 << SSP_PSP_EDYMSTOP_SHIFT,
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+ /* Frame Sync Relative Timing */
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+ SSP_PSP_FSRT = 1 << 25,
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+ /* Dummy Stop low bits */
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+ SSP_PSP_DMYSTOP_SHIFT = 23,
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+ SSP_PSP_DMYSTOP_MASK = 0x3 << SSP_PSP_DMYSTOP_SHIFT,
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+ /* Serial Frame Width */
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+ SSP_PSP_SFRMWDTH_SHIFT = 16,
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+ SSP_PSP_SFRMWDTH_MASK = 0x3f << SSP_PSP_SFRMWDTH_SHIFT,
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+ /* Serial Frame Delay */
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+ SSP_PSP_SFRMDLY_MASK = 0x7f,
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+ SSP_PSP_SFRMDLY_SHIFT = 9,
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+ /* Start Delay */
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+ SSP_PSP_STRTDLY_MASK = 0x7,
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+ SSP_PSP_STRTDLY_SHIFT = 4,
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+ /* End of Transfer Data State */
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+ SSP_PSP_ETDS = 1 << 3,
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+ /* Serial Frame Polarity */
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+ SSP_PSP_SFRMP = 1 << 2,
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+ /* Serial Clock Mode */
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+ SSP_PSP_SCMODE_SHIFT = 0,
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+ SSP_PSP_SCMODE_MASK = 0x3 << SSP_PSP_SCMODE_SHIFT,
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+
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+ SSP_PSP_RESERVED = 1 << 22,
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+};
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+
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+/* SSP TX Time Slot Active */
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+enum {
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+ SSP_SSTSA_EN = 1 << 8,
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+ SSP_SSTSA_MASK = 0xff,
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+};
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+
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+#endif /* __BROADWELL_I2S_H__ */
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